Abstract is missing.
- High-level synthesis - the right side of historyJason Anderson. 1 [doi]
- The configurable cloud - accelerating hyperscale datacenter services with FPGAsAndrew Putnam. 2 [doi]
- FPGA as service in public Cloud: Why and howYonghua Lin. 3 [doi]
- High density, low energy, magnetic tunnel junction based block RAMs for memory-rich FPGAsKosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz. 4-11 [doi]
- Analysis of transient voltage fluctuations in FPGAsDennis R. E. Gnad, Fabian Oboril, Saman Kiamehr, Mehdi Baradaran Tahoori. 12-19 [doi]
- An energy-efficient near/sub-threshold FPGA interconnect architecture using dynamic voltage scaling and power-gatingHe Qi, Oluseyi A. Ayorinde, Benton H. Calhoun. 20-27 [doi]
- Integer computations with soft GPGPU on FPGAsMuhammed Al Kadi, Michael Hübner. 28-35 [doi]
- Network-attached FPGAs for data center applicationsJagath Weerasinghe, Raphael Polig, François Abel, Christoph Hagleitner. 36-43 [doi]
- Hypervisor mechanisms to manage FPGA reconfigurable acceleratorsTian Xia, Jean-Christophe Prévotet, Fabienne Nouvel. 44-52 [doi]
- FPGA-based acceleration of FDAS module using OpenCLHaomiao Wang, Ming Zhang, Prabu Thiagaraj, Oliver Sinnen. 53-60 [doi]
- Automatic code generation of convolutional neural networks in FPGA implementationZhiqiang Liu, Yong Dou, Jingfei Jiang, Jinwei Xu. 61-68 [doi]
- An efficient implementation of online arithmeticYiren Zhao, John Wickerson, George A. Constantinides. 69-76 [doi]
- Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASICEriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr. 77-84 [doi]
- Random projections for scaling machine learning on FPGAsSean Fox, Stephen Tridgell, Craig T. Jin, Philip Heng Wai Leong. 85-92 [doi]
- High-speed regular expression matching with pipelined automataDenis Matousek, Jan Korenek, Viktor Pus. 93-100 [doi]
- Fine-grained module-based error recovery in FPGA-based TMR systemsZhuoran Zhao, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Çetin, Oliver Diessel. 101-108 [doi]
- Enhanced source-level instrumentation for FPGA in-system debug of High-Level Synthesis designsJose P. Pinilla, Steven J. E. Wilton. 109-116 [doi]
- A Programmable Configuration Controller for fault-tolerant applicationsLingkan Gong, Tong Wu, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Ediz Cetin, Oliver Diessel. 117-124 [doi]
- Tessellation-based multi-block memory mapping scheme for high-level synthesis with FPGAauJuan Escobedo, auMingjie Lin. 125-132 [doi]
- High-level synthesis of resource-shared microarchitectures from irregular complex C-codeBjörn Liebig, Andreas Koch 0001. 133-140 [doi]
- Spector: An OpenCL FPGA benchmark suiteQuentin Gautier, Alric Althoff, Pingfan Meng, Ryan Kastner. 141-148 [doi]
- Deflection routing for multi-level FPGA overlay NoCsKumar H. B. Chethan, Shubham Agarwal, Nachiket Kapre. 149-156 [doi]
- Hybrid hard NoCs for efficient FPGA communicationTianqi Liu, Naveen Kumar Dumpala, Russell Tessier. 157-164 [doi]
- Debugging framework for FPGA-based soft processorsDavid Sidler, Ken Eguro. 165-168 [doi]
- Dynamic scheduling of voter checks in FPGA-based TMR systemsNguyen T. H. Nguyen, Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel. 169-172 [doi]
- Energy-aware scheduling for task adaptive FPGAsWei Ting Loke, Chin Yang Koay. 173-176 [doi]
- Enriching C-based High-Level Synthesis with parallel pattern templatesLana Josipovic, Nithin George, Paolo Ienne. 177-180 [doi]
- Automatic wire modeling to explore novel FPGA architecturesGrace Zgheib, Paolo Ienne. 181-184 [doi]
- Rapid design space exploration for soft core processor customization and selectionDeshya Wijesundera, Alok Prakash, Thambipillai Srikanthan. 185-188 [doi]
- Application debug in FPGAs in the presence of multiple asynchronous clocksGeorgios Tzimpragos, Da Cheng, Stephanie Tapp, Balakrishna Jayadev, Amitava Majumdar. 189-192 [doi]
- Hardware Trojan avoidance and detection for dynamically re-configurable FPGAsNandeesh Veeranna, Benjamin Carrión Schäfer. 193-196 [doi]
- Dataflow design for optimal incremental SVM trainingShengjia Shao, Oskar Mencer, Wayne Luk. 197-200 [doi]
- FPGA acceleration of TreePM N-body simulations for Modified Newton DynamicsTianqi Wang, Linlin Zheng, Xi Jin, Bo Peng, Chuanjun Wang. 201-204 [doi]
- hCODE: An open-source platform for FPGA acceleratorsQian Zhao, Takuya Nakamichi, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 205-208 [doi]
- Fast polynomial arithmetic for Somewhat Homomorphic Encryption operations in hardware with Karatsuba algorithmVincent Migliore, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat. 209-212 [doi]
- FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAsJorge Echavarria, Stefan Wildermann, Andreas Becher, Jürgen Teich, Daniel Ziener. 213-216 [doi]
- Variable pipeline structure for Coarse Grained Reconfigurable Array CMANaoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano. 217-220 [doi]
- A survey of NoC evaluation platforms on FPGAsOtávio Alcântara de Lima Jr., Weslley N. Costa, Virginie Fresse, Frédéric Rousseau. 221-224 [doi]
- A modular architecture for dynamically reconfigurable middlebox with customized reconfiguration handlerTze Hon Tan, Chia Yee Ooi, Muhammad N. Marsono. 225-228 [doi]
- Exploring shared SRAM tables among NPN equivalent large LUTs in SRAM-based FPGAsAli Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid. 229-232 [doi]
- Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memoryNaifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao. 233-236 [doi]
- Design and implementation of open-source SATA III core for Stratix V FPGAsSumedh Guha, Wen Wang, Shafeeq Ibraheem, Mahesh Balakrishnan, Jakub Szefer. 237-240 [doi]
- Time-independent discrete Gaussian sampling for post-quantum cryptographyA. Khalid, J. Howe, C. Rafferty, M. O'Neill. 241-244 [doi]
- High performance Deformable Part Model accelerator based on FPGAQi Zhan, Min Gao, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang. 245-248 [doi]
- FPGA implementation of a real-time super-resolution system using a convolutional neural networkTaito Manabe, Yuichiro Shibata, Kiyoshi Oguri. 249-252 [doi]
- EMA-FPRMs: An efficient minimization algorithm for fixed polarity Reed-Muller expressionsZhenxue He, Limin Xiao, Longbing Zhang, Fei Gu, Zhisheng Huo, Mingfa Zhu, Li Ruan, Rui Liu, Xiang Wang. 253-256 [doi]
- An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming dataYuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi. 257-260 [doi]
- Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGAMaolin Wang, Ho-Cheung Ng, Bob M. F. Chung, B. Sharat Chandra Varma, Manish Kumar Jaiswal, Kevin K. Tsia, Ho Cheung Shum, Hayden Kwok-Hay So. 261-264 [doi]
- Caffeinated FPGAs: FPGA framework For Convolutional Neural NetworksRoberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi. 265-268 [doi]
- Hardware TCP Offload Engine based on 10-Gbps Ethernet for low-latency network communicationLi Ding, Ping Kang, Wenbo Yin, Linli Wang. 269-272 [doi]
- Fixed-ratio DXT format Frame Buffer Compressor for mobile graphics systemsYuzhi Zhou, Xi Jin, Tian Xiang. 273-276 [doi]
- A memory-based realization of a binarized deep convolutional neural networkHiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura. 277-280 [doi]
- FPGA based hardware accelerator for KAZE feature extraction algorithmLester Kalms, Ahmed Elhossini, Ben H. H. Juurlink. 281-284 [doi]
- IC security evaluation against fault injection attack based on FPGA emulationSong Xu, Qiang Liu, Tao Li, Hongxiang Fan. 285-288 [doi]
- An acceleration of a random forest classification using Altera SDK for OpenCLHiroki Nakahara, Akira Jinguji, Tomonori Fujii, Simpei Sato. 289-292 [doi]
- Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAsJakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek. 293-294 [doi]
- Random stimuli generation based on a stochastic context-free grammarOndrej Cekan, Jakub Podivinsky, Zdenek Kotásek. 295-296 [doi]
- Implementation of fault tolerant techniques into FPNNsMartin Krcma, Zdenek Kotásek, Jakub Lojda. 297-298 [doi]
- Evaluation of variable precision computing with variable precision FFT implementation on FPGAMengjun Li, Yongxin Zhu, Xu Wang, Tian Huang, Weida Chen, Bin Liu, Yishu Mao. 299-300 [doi]
- HLS-based fault tolerance approach for SRAM-based FPGAsJakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek. 301-302 [doi]
- SMCFA: A Zynq-based stacked multi CPU-FPGA architectureLin Li, Quansheng Yang. 303-306 [doi]
- A moving object extraction and classification system based on Zynq and IBM SuperVesselZhehao Li, Jifang Jin, Lingli Wang, Ji Yang, Jiahua Lu. 307-310 [doi]
- Implementation of parallel medical ultrasound imaging algorithm on CAPI-enabled FPGAJunying Chen, Shunfeng Zhou, HuaQing Min. 311-314 [doi]
- Asymmetric multiprocessing for motion control based on Zynq SoCXinyu Chen, Yong Gu, Chenxu Wang, Xuguang Guan. 315-318 [doi]
- Identification of Trax threats using pattern matchingDonald G. Bailey. 319-322 [doi]
- Trax solver on Zynq using incremental update algorithmHiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano. 323-326 [doi]
- Trax player implementation on FPGA using high level synthesis toolAkira Kojima. 327-330 [doi]