Table of Contents

• Power and the Future FPGA ArchitecturesSinan Kaptanoglu. [doi]
• GRAPE-DR Project: a combination of peta-scale computing and high-speed networkingKei Hiraki. [doi]
• Memory Footprint Reduction for FPGA Routing AlgorithmsScott Y. L. Chin, Steven J. E. Wilton. 1-8 [doi]
• SOC implementation of wave-pipelined circuitsGopalakrishnan Seetharaman, Balasubramanian Venkataramani. 9-16 [doi]
• Self-characterization of Combinatorial Circuit Delays in FPGAsJustin S. Wong, N. Pete Sedcole, Peter Y. K. Cheung. 17-23 [doi]
• FPGA Cluster Computing in the ETA Radio TelescopeCameron D. Patterson, Brian S. Martin, Steven W. Ellingson, John H. Simonetti, Sean E. Cutchin. 25-32 [doi]
• FPGA-based Accelerator Design for RankBoost in Web Search EnginesNing-Yi Xu, Xiongfei Cai, Rui Gao, Lei Zhang, Feng-hsiung Hsu. 33-40 [doi]
• Asymmetric Multi-Processor Architecture for Reconfigurable System-on-Chip and Operating System AbstractionsXin Xie, John A. Williams, Neil W. Bergmann. 41-48 [doi]
• Design and Implementation of an FPGA Architecture for High-Speed Network Feature ExtractionSailesh Pati, Ramanathan Narayanan, Gokhan Memik, Alok N. Choudhary, Joseph Zambreno. 49-56 [doi]
• Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow ClustersPeter Jamieson, Jonathan Rose. 57-64 [doi]
• A Method and FPGA Architecture for Real-Time Polymorphic ReconfigurationJason V. Paul, Samuel J. Stone, Yong C. Kim, Robert W. Bennington. 65-71 [doi]
• Reconfigurable Functional Units for Scientific Superscalar ProcessorsJonathan Evans, Kyle Rupnow, Katherine Compton. 73-80 [doi]
• A Coarse Grained Reconfigurable Architecture for Variable Block Size Motion EstimationRuchika Verma, Ali Akoglu. 81-88 [doi]
• Instrumented Multi-Stage Word-Length OptimizationWilliam G. Osborne, José Gabriel F. Coutinho, Ray C. C. Cheung, Wayne Luk, Oskar Mencer. 89-96 [doi]
• A Domain Specific Language for Reconfigurable Path-based Monte Carlo SimulationsDavid B. Thomas, Wayne Luk. 97-104 [doi]
• Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph ExtractionAlastair M. Smith, George A. Constantinides, Peter Y. K. Cheung. 105-112 [doi]
• Unifying FPGA Hardware DevelopmentJacob A. Bower, Wei Ning Cho, Wayne Luk. 113-120 [doi]
• Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPSTran Ngoc Thinh, Surin Kittitornkun, Shigenori Tomiyama. 121-128 [doi]
• High Performance Hardware Implementation of SpikeProp Learning: Potential and TradeoffsMarco Aurelio Nuño-Maganda, Miguel Arias-Estrada, Cesar Torres-Huitzil. 129-136 [doi]
• The Image Forest Transform ArchitectureFabio Augusto Cappabianco, Guido Araujo, Alexandre X. Falcão. 137-144 [doi]
• A Highly Parallel FPGA based IEEE-754 Compliant Double-Precision Binary Floating-Point Multiplication AlgorithmSandeep K. Venishetti, Ali Akoglu. 145-152 [doi]
• TAS-MRAM based Non-volatile FPGA logic circuitWeisheng Zhao, Eric Belhaire, Bernard Dieny, Guillaume Prenat, Claude Chappert. 153-160 [doi]
• Bitstream Decompression for High Speed FPGA Configuration from Slow MemoriesDirk Koch, Christian Beckhoff, Jürgen Teich. 161-168 [doi]
• Dynamic Intellectual Property Protection for Reconfigurable DevicesTim Güneysu, Bodo Möller, Christof Paar. 169-176 [doi]
• Hardware/Software Co-design of a General-Purpose Computation Platform in Particle PhysicsMing Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch, Shuo Yang, Tiago Perez, Zhen'An Liu. 177-183 [doi]
• Efficient and High-Throughput Implementations of AES-GCM on FPGAsGang Zhou, Harald Michalik, László Hinsenkamp. 185-192 [doi]
• A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGAMasato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Hideki Yamada, Hiroaki Kitano, Hideharu Amano. 193-200 [doi]
• An Approach for Applying Large Filters on Large Images using FPGAShingo Kawada, Tsutomu Maruyama. 201-208 [doi]
• Run-Time Management of Reconfigurable Hardware Tasks Using Embedded LinuxKrzysztof Kosciuszkiewicz, Fearghal Morgan, Krzysztof Kepa. 209-215 [doi]
• Implementations of Reconfigurable Logic Arrays on FPGAsTsutomu Sasao, Hiroki Nakahara. 217-223 [doi]
• Net Length based Routability Driven PackingAudip Pandit, Ali Akoglu. 225-232 [doi]
• FPGA-based Streaming Computation for Lattice Boltzmann MethodKentaro Sano, Oliver Pell, Wayne Luk, Satoru Yamamoto. 233-236 [doi]
• Reconfigurable Hardware Module Sequencer - A Tradeoff Between Networked and Data Flow ArchitecturesKai-Jung Shih, Chin-Chieh Hung, Pao-Ann Hsiung. 237-240 [doi]
• An Embedded Reconfigurable Logic Core based on Variable Grain Logic Cell ArchitectureYoshiaki Satou, Motoki Amagasaki, Hiroshi Miura, Kazunori Matsuyama, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi. 241-244 [doi]
• Improving Bounds for FPGA Logic MinimizationTim Todman, Haofan Fu, Oskar Mencer, Wayne Luk. 245-248 [doi]
• Floating-Point Matrix Multiplication in a Polymorphic ProcessorGeorgi Kuzmanov, Wouter M. van Oijen. 249-252 [doi]
• A Secure Digital Content Delivery System Based on Partially Reconfigurable HardwareYohei Hori, Hiroyuki Yokoyama, Hirofumi Sakane, Kenji Toda. 253-256 [doi]
• Productivity of High-Level Languages on Reconfigurable Computers: An HPC PerspectiveEsam El-Araby, Preetham Nosum, Tarek A. El-Ghazawi. 257-260 [doi]
• A Systolic Algorithm for the Quadratic Assignment Problem and its FPGA ImplementationYoshihiro Kimura, Shin'ichi Wakabayashi, Shinobu Nagayama. 261-264 [doi]
• Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architectureDaisaku Seto, Minoru Watanabe. 265-268 [doi]
• Efficient Mesh of Tree Interconnect for FPGA ArchitectureZied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez. 269-272 [doi]
• Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor ArraysSatoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Hideharu Amano. 273-276 [doi]
• An FPGA Based Travelling-Wave Fault Location SystemDavid P. Coggins, David W. P. Thomas, Barrie Hayes-Gill, Yiqun Zhu. 277-280 [doi]
• NICFlex: A Functional Verification Accelerator for An RTL NIC DesignXianyang Jiang, Xiaomin Li, Yue Tian, Kai Wang. 281-284 [doi]
• A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA ChipMasakazu Hioki, Takashi Kawanami, Yohei Matsumoto, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike, Toshiyuki Tsutsumi. 285-288 [doi]
• Optimal Buffering of FPGA Interconnect for Expected Delay OptimizationYi-Ru He, Wai-Kei Mak. 289-292 [doi]
• FPGA-Based 3-D engine for high-speed 3-D measurement based on light-section methodYusuke Yachide, Makoto Ikeda, Kunihiro Asada. 293-296 [doi]
• A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate arrayMao Nakajima, Minoru Watanabe. 297-300 [doi]
• Recursive Variable Expansion: A Loop Transformation for Reconfigurable SystemsZubair Nawaz, Ozana Silvia Dragomir, Thomas Marconi, Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis. 301-304 [doi]
• A Rapid Prototyping of Real-Time Pattern Generator for Step-and-Scan Lithography Using Digital Micromirror DeviceNaoto Miyamoto, Masahiko Shimakage, Tatsuo Morimoto, Kazuya Kadota, Shigetoshi Sugawa, Tadahiro Ohmi. 305-308 [doi]
• High Performance Software-Hardware Network Intrusion Detection SystemRyan B. Proudfoot, Kenneth B. Kent, Eric E. Aubanel, Nan Chen. 309-312 [doi]
• A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor NetworksHeiko Hinkelmann, Peter Zipf, Manfred Glesner. 313-316 [doi]
• FPGA Implementation of a Statically Reconfigurable Java Environment for Embedded SystemsShinsuke Nino, Takayuki Mori, Younghun Ko, Yuichiro Shibata, Kiyoshi Oguri. 317-320 [doi]
• A Dynamically Reconfigurable Architecture Combining Pixel-Level SIMD and Operation-Pipeline Modes for High Frame Rate Visual ProcessingNao Iwata, Shingo Kagami, Koichi Hashimoto. 321-324 [doi]
• A Balanced Vector-Quantization Processor Eliminating Redundant Calculation for Real-Time Motion Picture CompressionMasahiro Konda, Takahiro Nakayama, Naoto Miyamoto, Tadahiro Ohmi. 325-328 [doi]
• Real-Time Segmentation of Color Images based on the K-means Clustering on FPGATakashi Saegusa, Tsutomu Maruyama. 329-332 [doi]
• A Portable Memory Access Framework on Reconfigurable ComputersMiaoqing Huang, Ivan Gonzalez, Tarek A. El-Ghazawi. 333-336 [doi]
• The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex MIMO Instruction-Set ExtensionsCarlo Galuzzi, Koen Bertels, Stamatis Vassiliadis. 337-340 [doi]
• A Case for Soft Vector Processors in FPGAsJason Yu, Guy Lemieux. 341-344 [doi]
• A Portable Co-Verification System Which Generates Testbench AutomaticallyTakahito Nakajima, Shigeru Namiki, Shuhei Kinoshita, Naohiko Shimizu. 345-348 [doi]
• Multiply Accumulate Unit Optimised for Fast Dot-Product EvaluationWilliam Kamp, Andrew Bainbridge-Smith. 349-352 [doi]
• A Novel Network Architecture Support for Fast ReconfigurationJenny Yi-Chun Kuo, Hossam A. ElGindy, Anderson Kuei-An Ku. 353-356 [doi]
• A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable ProcessorsVu Manh Tuan, Hideharu Amano. 357-360 [doi]
• A Programmable Load/Store Unit on C-based Hardware Design for FPGAAkira Yamawaki, Masahiko Iwane. 361-364 [doi]
• An efficient FPGA-based implementation of Pollard's (ρ - 1) factorization algorithmDimitrios Meintanis, Ioannis Papaefstathiou. 365-368 [doi]
• A Novel Asynchronous e-FPGA Architecture for Security ApplicationsTaha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin, Sumanta Chaudhuri, Sylvain Guilley, Jean-Luc Danger, Philippe Hoogvorst. 369-372 [doi]
• A Multiprocessor System-on-Chip Implementation of a Laser-based Transparency Meter on an FPGAJames Dykes, Paulman Chan, Glenn H. Chapman, Lesley Shannon. 373-376 [doi]
• Compound Uniform Random Number Generators with On-Chhip Correlation and Distribution MeasurementsAmirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel. 377-380 [doi]
• Exploiting Slack Time in Dynamically Reconfigurable Processor ArchitecturesThomas Schweizer, Tobias Oppold, Julio A. de Oliveira Filho, Sven Eisenhardt, Kai Blocher, Wolfgang Rosenstiel. 381-384 [doi]