Surin Kittitornkun - researchr alias

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Viewing Publication 1 - 20 from 20

2021

Optimizing MultiStack Parallel (MSP) Sorting AlgorithmApisit Rattanatranurak, Surin Kittitornkun. jmm, 17(4):723-748, 2021. [doi]

2020

A MultiStack Parallel (MSP) Partition Algorithm Applied to SortingApisit Rattanatranurak, Surin Kittitornkun. jmm, 16(3):293-316, 2020. [doi]

2017

A Spatio-Temporal malware and country clustering algorithm: 2012 IIJ MITF case studyKhamphao Sisaat, Surin Kittitornkun, Hiroaki Kikuchi, Chaxiong Yukonhiatou, Masato Terada, Hiroshi Ishii. ijisec, 16(5):459-473, 2017. [doi]

2016

Parallel Partition and Merge QuickSort (PPMQSort) on Multicore CPUsRatthaslip Ranokphanuwat, Surin Kittitornkun. tjs, 72(3):1063-1091, 2016. [doi]

2013

Time Zone Correlation Analysis of Malware/Bot DownloadsKhamphao Sisaat, Hiroaki Kikuchi, Shunji Matsuo, Masato Terada, Masashi Fujiwara, Surin Kittitornkun. ieicet, 96-B(7):1753-1763, 2013. [doi]

2012

Geographical Visualization of Malware Download for Anomaly DetectionN. Hiroguchi, Hiroaki Kikuchi, Khamphao Sisaat, Surin Kittitornkun. asiajcis 2012: 74-78 [doi]

2010

Massively Parallel Cuckoo Pattern Matching Applied for NIDS/NIPSThinh Ngoc Tran, Surin Kittitornkun. delta 2010: 217-221 [doi]

2009

PAMELA: Pattern Matching Engine with Limited-Time Update for NIDS/NIPSThinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama. ieicet, 92-D(5):1049-1061, 2009. [doi]

2007

Applying Cuckoo Hashing for FPGA-based Pattern Matching in NIDS/NIPSTran Ngoc Thinh, Surin Kittitornkun, Shigenori Tomiyama. fpt 2007: 121-128 [doi]

FPGA-Based Cuckoo Hashing for Pattern Matching in NIDS/NIPSThinh Ngoc Tran, Surin Kittitornkun. apnoms 2007: 334-343 [doi]

2006

MT-ClustalW: multithreading multiple sequence alignmentK. Chaichoompu, Surin Kittitornkun, Sissades Tongsima. ipps 2006: [doi]

Manifold similarity search of DNA sequences with reconfigurable hardwareThinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama. fpga 2006: 231 [doi]

2003

Mapping deep nested do-loop DSP algorithms to large scale FPGA array structuresSurin Kittitornkun, Yu Hen Hu. tvlsi, 11(2):208-217, 2003. [doi]

Processor Array Synthesis from Shift-Variant Deep Nested Do LoopsSurin Kittitornkun, Yu Hen Hu. tjs, 24(3):229-249, 2003. [doi]

Supersystolic arrays on large-scale FPGA structuresSurin Kittitornkun, Yu Hen Hu. iscas 2003: 756-759 [doi]

2001

Efficient Implementation of Nested-Loop Multimedia AlgorithmsSurin Kittitornkun, Yu Hen Hu. ejasp, 2001(3):129-146, 2001. [doi]

Frame-level pipelined motion estimation array processorSurin Kittitornkun, Yu Hen Hu. tcsv, 11(2):248-251, 2001.

Low bit rate video sequence coding artifact removalSeungjoon Yang, Surin Kittitornkun, Yu Hen Hu, Truong Q. Nguyen, Damon L. Tull. mmsp 2001: 53-58 [doi]

2000

Data Partitioning and Reversible Variable Length Codes for Robust Video CommunicationsAdam H. Li, Surin Kittitornkun, Yu Hen Hu, Dong-Seek Park, John D. Villasenor. dcc 2000: 460-469 [doi]

Blocking Artifact Free Inverse Discrete Cosine TransformSeungjoon Yang, Surin Kittitornkun, Yu Hen Hu, Truong Q. Nguyen, Damon L. Tull. icip 2000: 869-872

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