Table of Contents

• A 90nm low-power FPGA for battery-powered applicationsTim Tuan, Sean Kao, Ahmad Arif Rahman, Satyaki Das, Steven Trimberger. 3-11 [doi]
• Embedded floating-point units in FPGAsMichael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert. 12-20 [doi]
• Measuring the gap between FPGAs and ASICsIan Kuon, Jonathan Rose. 21-30 [doi]
• Optimality study of logic synthesis for LUT-based FPGAsJason Cong, Kirill Minkovich. 33-40 [doi]
• Improvements to technology mapping for LUT-based FPGAsAlan Mishchenko, Satrajit Chatterjee, Robert K. Brayton. 41-49 [doi]
• Improving performance and robustness of domain-specific CPLDsMark Holland, Scott Hauck. 50-59 [doi]
• Design, implementation, and verification of active cache emulator (ACE)Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu. 63-72 [doi]
• Modeling the data-dependent performance of pattern-matching architecturesChristopher R. Clark, David E. Schimmel. 73-82 [doi]
• An iterative division algorithm for FPGAsJianhua Liu, Michael Chang, Chung-Kuan Cheng. 83-89 [doi]
• Yield enhancements of design-specific FPGAsNicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko. 93-100 [doi]
• FPGA clock network architecture: flexibility vs. area and powerJulien Lamoureux, Steven J. E. Wilton. 101-108 [doi]
• Performance benefits of monolithically stacked 3D-FPGAMingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wong. 113-122 [doi]
• Magnetic tunnelling junction based FPGANicolas Bruchon, Lionel Torres, Gilles Sassatelli, Gaston Cambon. 123-130 [doi]
• A reconfigurable architecture for hybrid CMOS/Nanodevice circuitsDmitri B. Strukov, Konstantin Likharev. 131-140 [doi]
• A reconfigurable hardware based embedded scheduler for buffered crossbar switchesLotfi Mhamdi, Christopher Kachris, Stamatis Vassiliadis. 143-149 [doi]
• An adaptive Reed-Solomon errors-and-erasures decoderLilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier. 150-158 [doi]
• A compact FPGA implementation of the hash function whirlpoolNorbert Pramstaller, Christian Rechberger, Vincent Rijmen. 159-166 [doi]
• Armada: timing-driven pipeline-aware routing for FPGAsKenneth Eguro, Scott Hauck. 169-178 [doi]
• Combining module selection and resource sharing for efficient FPGA pipeline synthesisWelson Sun, Michael J. Wirthlin, Stephen Neuendorffer. 179-188 [doi]
• Power-aware RAM mapping for FPGA embedded memory blocksRussell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy. 189-198 [doi]
• Application-specific customization of soft processor microarchitecturePeter Yiannacouras, J. Gregory Steffan, Jonathan Rose. 201-210 [doi]
• Fast and accurate resource estimation of automatically generated custom DFT IP coresPeter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel. 211-220 [doi]
• Evaluation of granularity on threshold voltage control in flex power FPGAMasakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike. 223 [doi]
• FPGAs with multidimensional mesh topologyYohei Matsumoto, Hanpei Koike, Akira Masaki. 223 [doi]
• A novel methodology for designing high-performance and low-energy FPGA routing architectureK. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis. 224 [doi]
• Autonomous-repair cell for fault tolerant dynamic-reconfigurable devicesKentaro Nakahara, Shin ichi Kouyama, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura. 224 [doi]
• A programmable majority logic array using molecular scale electronicsGarrett S. Rose, Mircea R. Stan. 225 [doi]
• A multilevel hierarchical interconnection structure for FPGAHayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez. 225 [doi]
• Test and recovery for fine-grained nanoscale architecturesMohammad Tehranipoor, Reza M. Rad. 226 [doi]
• Fine-grained island style architecture for molecular electronic devicesMohammad Tehranipoor, Reza M. Rad. 226 [doi]
• Post-placement interconnect entropyWenyi Feng, Jonathan Greene. 227 [doi]
• A type architecture for hybrid micro-parallel computersBenjamin Ylvisaker, Brian Van Essen, Carl Ebeling. 227 [doi]
• Testing embedded RAM modules in SRAM-based FPGAsMohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali. 228 [doi]
• Jaguar: a compiler infrastructure for Java reconfigurable computingYoungsun Han, Seokjoong Hwang, Seon Wook Kim. 228 [doi]
• Effective clustering technique to optimize routability of outer cluster netsMasaki Kobata, Masahiro Iida, Toshinori Sueyoshi. 229 [doi]
• Configuration tools for a new multilevel hierarchical FPGAZied Marrakchi, Hayder Mrabet, Habib Mehrez. 229 [doi]
• Simulative analysis of dynamic scheduling heuristics for reconfigurable computing of parallel applicationsRajagopal Subramaniyan, Ian A. Troxel, Alan D. George, Melissa Smith. 230 [doi]
• High speed FIR filter implementation using add and shift methodShahnam Mirzaei, Anup Hosangadi, Ryan Kastner. 231 [doi]
• Manifold similarity search of DNA sequences with reconfigurable hardwareThinh Ngoc Tran, Surin Kittitornkun, Shigenori Tomiyama. 231 [doi]
• A real-time implementation of Richardson-Lucy deconvolutionOliver Sims, James Irvine. 232 [doi]
• The routability of multiprocessor network topologies in FPGAsManuel Saldaña, Lesley Shannon, Paul Chow. 232 [doi]
• FPGA based RAID 6 hardware acceleratorMichael Gilroy, James Irvine, William Berrie. 232 [doi]
• Building a flexible and scalable DRAM interface for networking applications on FPGAsJike Chong, Chidamber Kulkarni, Gordon J. Brebner. 233 [doi]
• A generic lookup cache architecture for network processing applicationsJanardhan Singaraju, John A. Chandy. 233 [doi]
• Efficient use of communications between an FPGA s embedded processor and its reconfigurable logicJoshua Noseworthy, Miriam Leeser. 233 [doi]
• A Performance model for accelerating scientific applications on reconfigurable computersRonald Scrofano, Viktor K. Prasanna. 234 [doi]
• Periodic licensing of FPGA based intellectual propertyNathaniel Couture, Kenneth B. Kent. 234 [doi]
• Reconfigurable computing with multiscale data fusion for remote sensingVikas Aggarwal, Alan D. George, K. Clint Slatton. 235 [doi]
• A reconfigurable architecture for network intrusion detection using principal component analysisDavid T. Nguyen, Gokhan Memik, Alok N. Choudhary. 235 [doi]
• Flexible implementation of genetic algorithms on FPGAsTatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito. 236 [doi]
• GSFAP adaptive filtering using log arithmetic for resource-constrained embedded systemsMilan Tichý, Andy Nisbet, David Gregg. 236 [doi]
• Context-free-grammar based token tagger in reconfigurable devicesYoung H. Cho, James Moscola, John W. Lockwood. 237 [doi]