Antonios Thanailakis - researchr alias

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Viewing Publication 1 - 23 from 23

2010

A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA ArchitecturesKostas Siozios, Dimitrios Soudris, Antonios Thanailakis. jcsc, 19(3):701-717, 2010. [doi]

2008

Designing a General-Purpose Interconnection Architecture for Field Programmable Gate ArraysKostas Siozios, Dimitrios Soudris, Antonios Thanailakis. jolpe, 4(1):34-47, 2008. [doi]

2007

Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinementStylianos Mamagkakis, Alexandros Bartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. jsa, 53(7):417-436, 2007. [doi]

Designing Heterogeneous FPGAs with Multiple SBsKostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis. arc 2007: 91-96 [doi]

2006

Dynamic data type refinement methodology for systematic performance-energy design exploration of network applicationsAlexandros Bartzas, Stylianos Mamagkakis, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. date 2006: 740-745 [doi]

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable ProcessorsNikolas Kroupis, Nikolaos D. Zervas, Minas Dasygenis, Konstantinos Tatas, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis. vlsisp, 44(1-2):153-171, 2006. [doi]

Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performanceStylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. comcom, 29(13-14):2612-2620, 2006. [doi]

Efficient Power Management Strategy of FPGAs Using a Novel Placement TechniqueKostas Siozios, Dimitrios Soudris, Antonios Thanailakis. vlsi 2006: 204-209 [doi]

A novel methodology for designing high-performance and low-energy FPGA routing architectureK. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis. fpga 2006: 224 [doi]

Designing Alternative FPGA Implementations Using Spatial Data from Hardware ResourcesKostas Siozios, Dimitrios Soudris, Antonios Thanailakis. patmos 2006: 403-414 [doi]

2005

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy BottleneckMinas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. date 2005: 946-947 [doi]

Improving the Memory Bandwidth Utilization Using Loop TransformationsMinas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. patmos 2005: 117-126 [doi]

A Modified Spiral Search Algorithm and its Embedded Hardware ImplementationNikolas Kroupis, Minas Dasygenis, Dimitrios Soudris, Antonios Thanailakis. wec 2005: 375-378

Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network ApplicationsStylianos Mamagkakis, Christos Baloukas, David Atienza, Francky Catthoor, Dimitrios Soudris, José M. Mendías, Antonios Thanailakis. wwic 2005: 354-364 [doi]

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing ApplicationsKostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos. ieicet, 88-D(7):1369-1380, 2005. [doi]

2004

Power, Performance and Area Exploration for Data Memory Assignment of Multimedia ApplicationsMinas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. samos 2004: 540-549 [doi]

Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement MethodologyStylianos Mamagkakis, Alexandros Mpartzas, Georgios Pouiklis, David Atienza, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias, Antonios Thanailakis. wwic 2004: 26-37 [doi]

A reusable IP FFT core for DSP applicationsEvaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis. iscas 2004: 621-624 [doi]

Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gateIoannis Tsimperidis, Ioannis Karafyllidis, Antonios Thanailakis. mj, 35(5):471-478, 2004. [doi]

2003

Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithmsKonstantinos Tatas, Minas Dasygenis, Nikolas Kroupis, Antonios Argyriou, Dimitrios Soudris, Antonios Thanailakis. rti, 9(6):371-386, 2003. [doi]

2001

Power, performance and area exploration of block matching algorithms mapped on programmable processorsNikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis. icip 2001: 728-731 [doi]

1996

A hybrid cellular automaton/neural network classifier for multi-valued patterns and its VLSI implementationPanagiotis Tzionas, Antonios Thanailakis, Phillipos Tsalides. integration, 20(2):211-237, 1996. [doi]

1993

2-Dimensional minimum cost path planning using a cellular automaton architecturePanagiotis Tzionas, Phillipos Tsalides, Antonios Thanailakis. integration, 16(2):179-194, 1993. [doi]

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Publications by 'Antonios Thanailakis'

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Publications by 'Antonios Thanailakis'

Viewing Publication 1 - 23 from 23

2010

2008

2007

2006

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2001

1996

1993

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