Abstract is missing.
- The Molen Programming ParadigmStamatis Vassiliadis, Georgi Gaydadjiev, Koen Bertels, Elena Moscu Panainte. 1-10 [doi]
- Loading rho-µ-Code: Design ConsiderationsGeorgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis. 11-19 [doi]
- RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon SystemsStéphane Chevobbe, Nicolas Ventroux, Frédéric Blanc, Thierry Collette. 20-29 [doi]
- Basic OS Support for Distributed Reconfigurable HardwareChristian Haubelt, Dirk Koch, Jürgen Teich. 30-38 [doi]
- A Cost-Efficient RISC Processor Platform for Real Time Audio ApplicationsJens Peter Wittenburg, Ulrich Schreiber, Ulrich Gries, Markus Schneider 0003, Tim Niggemeier. 39-48 [doi]
- Customising Processors: Design-Time and Run-Time OpportunitiesWayne Luk. 49-58 [doi]
- Intermediate Level Components for Reconfigurable PlatformsErwan Fabiani, Christophe Gouyen, Bernard Pottier. 59-68 [doi]
- Performance Estimation of Streaming Media Applications for Reconfigurable PlatformsCarsten Reuter, Javier Martín-Langerwerf, Hans-Joachim Stolberg, Peter Pirsch. 69-77 [doi]
- CoDeL: Automatically Synthesizing Network Interface ControllersRadhakrishnan Sivakumar, Vassilios V. Dimakopoulos, Nikitas J. Dimopoulos. 78-87 [doi]
- with Wide Functional UnitsMiquel Pericàs, Eduard Ayguadé, Javier Zalamea, Josep Llosa, Mateo Valero. 88-97 [doi]
- An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCsUlrich Heinkel, Claus Mayer, Charles F. Webb, Hans Sahm, Werner Haas, Stefan Gossens. 98-107 [doi]
- Register-Based Permutation Networks for Stride PermutationsTuomas Järvinen, Jarmo Takala. 108-117 [doi]
- A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier StructuresDavid Guevorkian, Petri Liuha, Aki Launiainen, Ville Lappalainen. 118-127 [doi]
- Metrics for Digital Signal Processing Architectures Characterization: Remanence and ScalabilityPascal Benoit, Gilles Sassatelli, Lionel Torres, Didier Demigny, Michel Robert, Gaston Cambon. 128-137 [doi]
- Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip DesignsTim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 138-148 [doi]
- Comparison of Data Dependence Analysis TestsMiia Viitanen, Timo D. Hämäläinen. 149-158 [doi]
- MOUSE: A Shortcut from Matlab Source to SIMD DSP Assembly CodeGordon Cichon, Gerhard Fettweis. 159-167 [doi]
- High-Level Energy Estimation for ARM-Based SOCsDan Crisu, Sorin Cotofana, Stamatis Vassiliadis, Petri Liuha. 168-177 [doi]
- IDF Models for Trace Transformations: A Case Study in Computational RefinementCagkan Erbas, Simon Polstra, Andy D. Pimentel. 178-190 [doi]
- Programming Extremely Flexible PlatformsKees A. Vissers. 191 [doi]
- The Virtex II Pro:::TM::: MOLEN ProcessorGeorgi Kuzmanov, Georgi Gaydadjiev, Stamatis Vassiliadis. 192-202 [doi]
- Reconfigurable Hardware for a Scalable Wavelet Video Decoder and Its Performance RequirementsDirk Stroobandt, Hendrik Eeckhaut, Harald Devos, Mark Christiaens, Fabio Verdicchio, Peter Schelkens. 203-212 [doi]
- Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning TechniquesPedro C. Diniz. 213-223 [doi]
- Modeling Loop Unrolling: Approaches and Open IssuesJoão M. P. Cardoso, Pedro C. Diniz. 224-233 [doi]
- Self-loop Pipelining and Reconfigurable Dataflow ArraysJoão M. P. Cardoso. 234-243 [doi]
- Architecture Exploration for 3G Telephony Applications Using a Hardware-Software Prototyping PlatformFrançois Charot, Madeleine Nyamsi, Patrice Quinton, Charles Wagner. 244-253 [doi]
- Embedded Context Aware Hardware Component Generation for Dataflow System ExplorationJohn McAllister, Roger Woods, Richard Walke. 254-263 [doi]
- On the (Re-)Use of IP-Components in Re-configurable PlatformsJérôme Lemaitre, Sylvain Alliot, Ed F. Deprettere. 264-273 [doi]
- Customising Hardware Designs for Elliptic Curve CryptographyNicolas Telle, Wayne Luk, Ray C. C. Cheung. 274-283 [doi]
- Dynamic Hardware Reconfigurations: Performance Impact for MPEG2Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis. 284-292 [doi]
- Compiler and System Techniques for soc Distributed Reconfigurable AcceleratorsJoel Cambonie, Sylvain Guérin, Ronan Keryell, Loïc Lagadec, Bernard Pottier, Olivier Sentieys, Bernt Weber, Samar Yazdani. 293-302 [doi]
- Design Space Exploration with Automatic Selection of SW and HW for Embedded ApplicationsJúlio C. B. de Mattos, Antonio Carlos Schneider Beck, Luigi Carro, Flávio Rech Wagner. 303-312 [doi]
- On Enhancing SIMD-Controlled DSPs for Performing Recursive FilteringMichael Hosemann, Gerhard Fettweis. 313-322 [doi]
- Memory Bandwidth Requirements of Tile-Based RenderingIosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha. 323-332 [doi]
- Using CoDeL to Rapidly Prototype Network Processsor ExtensionsNainesh Agarwal, Nikitas J. Dimopoulos. 333-342 [doi]
- Synchronous Transfer Architecture (STA)Gordon Cichon, Pablo Robelly, Hendrik Seidel, Emil Matús, Marcus Bronzel, Gerhard Fettweis. 343-352 [doi]
- Generated DSP Cores for Implementation of an OFDM Communication SystemHendrik Seidel, Emil Matús, Gordon Cichon, Pablo Robelly, Marcus Bronzel, Gerhard Fettweis. 353-362 [doi]
- A Novel Data-Path for Accelerating DSP KernelsMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis. 363-372 [doi]
- Scalable FFT Processors and Pipelined Butterfly UnitsJarmo Takala, Konsta Punkka. 373-382 [doi]
- Scalable Instruction-Level Parallelism.Chris R. Jesshope. 383-392 [doi]
- A Low-Power Multithreaded Processor for Baseband Communication SystemsMichael J. Schulte, C. John Glossner, Suman Mamidi, Mayan Moudgill, Stamatis Vassiliadis. 393-402 [doi]
- Initial Evaluation of Multimedia Extensions on VLIW ArchitecturesEsther Salamí, Mateo Valero. 403-412 [doi]
- HIBI v.2 Communication Network for System-on-ChipErno Salminen, Vesa Lahtinen, Tero Kangas, Jouni Riihimäki, Kimmo Kuusilinna, Timo D. Hämäläinen. 413-422 [doi]
- DIF: An Interchange Format for Dataflow-Based Design ToolsChia-Jui Hsu, Fuat Keceli, Ming-Yung Ko, Shahrooz Shahparnia, Shuvra S. Bhattacharyya. 423-432 [doi]
- Scalable and Modular SchedulingPaul Feautrier. 433-442 [doi]
- Early ISS Integration into Network-on-Chip DesignsAndreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 443-452 [doi]
- Cycle Accurate Simulation Model Generation for SoC PrototypingAntoine Fraboulet, Tanguy Risset, Antoine Scherrer. 453-462 [doi]
- Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler RetargetingJianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun. 463-473 [doi]
- A Communication-Centric Design Flow for HIBI-Based SoCsTero Kangas, Jouni Riihimäki, Erno Salminen, Vesa Lahtinen, Heikki Orsila, Kimmo Kuusilinna, Timo D. Hämäläinen. 474-483 [doi]
- Performance Analysis of SoC Communication by Application of Deterministic and Stochastic Petri NetsHolger Blume, Thorsten von Sydow, Tobias G. Noll. 484-493 [doi]
- Communication Optimization in Compaan Process NetworksIoan Cimpian, Alexandru Turjan, Ed F. Deprettere, Erwin A. de Kock. 494-506 [doi]
- Analysis of Dataflow Programs with Interval-Limited Data-RatesJürgen Teich, Shuvra S. Bhattacharyya. 507-518 [doi]
- High-Speed Event-Driven RTL Compiled SimulationAlexey Kupriyanov, Frank Hannig, Jürgen Teich. 519-529 [doi]
- A High-Level Programming Paradigm for SystemCMark Thompson, Andy D. Pimentel. 530-539 [doi]
- Power, Performance and Area Exploration for Data Memory Assignment of Multimedia ApplicationsMinas Dasygenis, Erik Brockmeyer, Bart Durinck, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis. 540-549 [doi]
- Constraints Derivation and Propagation for Large-Scale Embedded Systems ExplorationLaurentiu Nicolae, Ed F. Deprettere. 550-560 [doi]