Abstract is missing.
- Accelerating Image Analysis for Localization Microscopy with FPGAsFrederik Grüll, Manfred Kirchgessner, Rainer Kaufmann, Michael Hausmann, Udo Kebschull. 1-5 [doi]
- Unifying Finite Difference Option-Pricing for Hardware AccelerationQiwei Jin, Wayne Luk, David B. Thomas. 6-9 [doi]
- Leros: A Tiny Microcontroller for FPGAsMartin Schoeberl. 10-14 [doi]
- Design of a High Switching Frequency FPGA-Based SPWM Generator for DC/AC InvertersMatina Lakka, Eftichios Koutroulis, Apostolos Dollas. 15-19 [doi]
- A New Process Characterization Method for FPGAs Based on Electromagnetic AnalysisFlorent Bruguier, Pascal Benoit, Philippe Maurine, Lionel Torres. 20-23 [doi]
- An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code CoprocessorsJack Sampson, Manish Arora, Nathan Goulding-Hotta, Ganesh Venkatesh, Jonathan Babb, Vikram Bhatt, Steven Swanson, Michael Bedford Taylor. 24-29 [doi]
- A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAsHarry Sidiropoulos, Kostas Siozios, Dimitrios Soudris. 30-33 [doi]
- Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic MemoryTakahiro Watanabe, Minoru Watanabe. 34-37 [doi]
- An FPGA Solver for SAT-Encoded Formal Verification ProblemsKenji Kanazawa, Tsutomu Maruyama. 38-43 [doi]
- FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population ActivitiesWill X. Y. Li, Rosa H. M. Chan, Wei Zhang, C. W. Yu, Ray C. C. Cheung, Dong Song, Theodore W. Berger. 44-49 [doi]
- Accelerating Fluid Registration Algorithm on Multi-FPGA PlatformsJason Cong, Muhuan Huang, Yi Zou. 50-57 [doi]
- Latch-Based Performance Optimization for FPGAsBill Teng, Jason Helge Anderson. 58-63 [doi]
- XDL-Based Module Generators for Rapid FPGA Design ImplementationSubhrashankha Ghosh, Brent E. Nelson. 64-69 [doi]
- Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic NetworksRehan Ahmed, Peter Hallschmid. 70-75 [doi]
- A Radix Tree Router for Scalable FPGA NetworksWilliam V. Kritikos, Yamuna Rajasekhar, Andrew G. Schmidt, Ron Sass. 76-81 [doi]
- Generic Low-Latency NoC Router Architecture for FPGA Computing SystemsYe Lu, John V. McCanny, Sakir Sezer. 82-89 [doi]
- Scalable Arbiters and Multiplexers for On-FGPA Interconnection NetworksGiorgos Dimitrakopoulos, Christoforos Kachris, Emmanouil Kalligeros. 90-96 [doi]
- 20Gbps C-Based Complex Event ProcessingHiroaki Inoue, Takashi Takenaka, Masato Motomura. 97-102 [doi]
- Embedded Systems Start-Up under Timing Constraints on Modern FPGAsJoachim Meyer, Juanjo Noguera, Michael Hübner, Rodney Stewart, Jürgen Becker. 103-109 [doi]
- Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL MethodYuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang. 110-115 [doi]
- A Run-Time Adaptive FPGA Architecture for Monte Carlo SimulationsXiang Tian, Christos-Savvas Bouganis. 116-122 [doi]
- Precore - A Token-Based Speculation Architecture for High-Level Language to Hardware CompilationBenjamin Thielmann, Jens Huthmann, Andreas Koch 0001. 123-129 [doi]
- Implementing Stream-Processing Applications on FPGAs: A DSL-Based ApproachJocelyn Sérot, François Berry, Sameer Ahmed. 130-137 [doi]
- Revisiting the Newton-Raphson Iterative Method for Decimal DivisionMário P. Véstias, Horácio C. Neto. 138-143 [doi]
- Hardware Support for Broadcast and Reduce in MPSoCYuanxi Peng, Manuel Saldaña, Paul Chow. 144-150 [doi]
- The Impact of Aging on an FPGA-Based Physical Unclonable FunctionAbhranil Maiti, Logan McDougall, Patrick Schaumont. 151-156 [doi]
- An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene OperatorsYoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama. 157-161 [doi]
- Multi-module Hashing System for SHA-3 & FPGA IntegrationNicolas Sklavos. 162-166 [doi]
- FPGA-Accelerated Object Detection Using Edge InformationChristos Kyrkou, Christos Ttofis, Theocharis Theocharides. 167-170 [doi]
- Memory-Efficient and Fast Run-Time Reconfiguration of Regularly Structured DesignsBrahim Al Farisi, Karel Heyse, Karel Bruneel, Dirk Stroobandt. 171-176 [doi]
- A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable HardwareJuan Antonio Clemente, Vincenzo Rana, Donatella Sciuto, Ivan Beretta, David Atienza. 177-180 [doi]
- RAMPSoCVM: Runtime Support and Hardware Virtualization for a Runtime Adaptive MPSoCDiana Göhringer, Stephan Werner, Michael Hübner, Jürgen Becker. 181-184 [doi]
- Memory Virtualization for Multithreaded Reconfigurable HardwareAndreas Agne, Marco Platzner, Enno Lübbers. 185-188 [doi]
- Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable ArchitecturesHiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye. 189-194 [doi]
- ERDB: An Embedded Routing Database for Reconfigurable SystemsKrzysztof Kepa, Fearghal Morgan, Peter Athanas. 195-200 [doi]
- Clustered Hierarchical Search Structure for Large-Scale Packet Classification on FPGAOguzhan Erdem, Hoang Le, Viktor K. Prasanna. 201-206 [doi]
- Thwarting Software Attacks on Data-Intensive Platforms with Configurable Hardware-Assisted Application Rule EnforcementMohammed M. Farag, Lee W. Lerner, Cameron D. Patterson. 207-212 [doi]
- Towards On-the-Fly Incremental Updates for Virtualized Routers on FPGAThilan Ganegedara, Hoang Le, Viktor K. Prasanna. 213-218 [doi]
- An Implementation of the Mean Shift Filter on FPGADang Ba Khac Trieu, Tsutomu Maruyama. 219-224 [doi]
- Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAsHadi Parandeh-Afshar, Paolo Ienne. 225-231 [doi]
- FPGA-Specific Arithmetic Optimizations of Short-Latency AddersHong Diep Nguyen, Bogdan Pasca, Thomas B. Preußer. 232-237 [doi]
- A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAsHarry Sidiropoulos, Kostas Siozios, Dimitrios Soudris. 238-243 [doi]
- FlexCache: Field Extensible Cache Controller Architecture Using On-chip Reconfigurable FabricDaniel Lo, Greg Malysa, G. Edward Suh. 244-251 [doi]
- VPFPAP: A Special-Purpose VLIW Processor for Variable-Precision Floating-Point ArithmeticYuanwu Lei, Yong Dou, Jie Zhou, Sufeng Wang. 252-257 [doi]
- A Dynamically-Reconfigurable Phased Array Radar Processing SystemEmmanuel Seguin, Russell Tessier, Eric J. Knapp, Robert W. Jackson. 258-263 [doi]
- Exploitation of Parallel Search Space Evaluation with FPGAs in Combinatorial Problems: The Eternity II CasePavlos Malakonakis, Apostolos Dollas. 264-268 [doi]
- A Novel Power Reduction Technique for Block Matching Motion Estimation HardwareAbdulkadir Akin, Onur Can Ulusel, Tevfik Zafer Ozcan, Gokhan Sayilar, Ilker Hamzaoglu. 269-272 [doi]
- A Comparison on FPGA of Modular Multipliers Suitable for Elliptic Curve Cryptography over GF(p) for Specific p ValuesMark Hamilton, William P. Marnane, Arnaud Tisserand. 273-276 [doi]
- Stress-Aware Module Placement on Reconfigurable DevicesJosef Angermeier, Daniel Ziener, Michael Glaß, Jürgen Teich. 277-281 [doi]
- Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis AlgorithmsNaifeng Jing, Ju-Yueh Lee, Zhe Feng 0002, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He. 282-285 [doi]
- A Routing Architecture for Mapping Dataflow Graphs at Run-TimeDirk Koch, Jim Torresen. 286-290 [doi]
- An Easily Testable Routing Architecture and Efficient Test TechniqueKazuki Inoue, Hiroki Yosho, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi. 291-294 [doi]
- Methods and Mechanisms for Hardware Multitasking: Executing and Synchronizing Fully Relocatable Hardware Tasks in Xilinx FPGAsXabier Iturbe, Khaled Benkrid, Tughrul Arslan, Raul Torrego, Imanol Martinez. 295-300 [doi]
- Performance Failure Prediction Using Built-In Delay Sensors in FPGAsVasco Bexiga, Carlos Leong, Jorge Semião, Isabel C. Teixeira, João Paulo Teixeira, María Dolores Valdés, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas. 301-304 [doi]
- A Model for Matrix Multiplication Performance on FPGAsColin Yu Lin, Hayden Kwok-Hay So, Philip Heng Wai Leong. 305-310 [doi]
- Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGAYong Cheol Peter Cho, Sungmin Bae, Yongseok Jin, Kevin M. Irick, Vijaykrishnan Narayanan. 311-316 [doi]
- High Frequency Trading Acceleration Using FPGAsChristian Leber, Benjamin Geib, Heiner Litz. 317-322 [doi]
- Improving FPGA Reliability with Wear-LevellingEdward A. Stott, Peter Y. K. Cheung. 323-328 [doi]
- A Low-Cost Sensor for Aging and Late Transitions Detection in Modern FPGAsAbdulazim Amouri, Mehdi Baradaran Tahoori. 329-335 [doi]
- Reducing FPGA Router Run-Time through Algorithm and ArchitectureMarcel Gort, Jason Helge Anderson. 336-342 [doi]
- Fast RTL Power Estimation for FPGA DesignsPaul Schumacher, Pradip Jha, Sudha Kuntur, Tim Burke, Alan Frost. 343-348 [doi]
- RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAsChristopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent E. Nelson, Brad L. Hutchings. 349-355 [doi]
- Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore SystemMichel A. Kinsy, Michael Pellauer, Srinivas Devadas. 356-362 [doi]
- Separable FIR Filtering in FPGA and GPU Implementations: Energy, Performance, and Accuracy ConsiderationsDaniel Llamocca, Cesar Carranza, Marios S. Pattichis. 363-368 [doi]
- Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video CodecsAndrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo Marrero Callicó, Roberto Sarmiento. 369-375 [doi]
- Compact Hardware Architecture for Hummingbird Cryptographic AlgorithmIsmail San, Nuray At. 376-381 [doi]
- Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDICSurapong Pongyupinpanich, Manfred Glesner. 382-384 [doi]
- Failure Probability and Fault Observability of SRAM-FPGA SystemsCinzia Bernardeschi, Luca Cassano, Andrea Domenici. 385-388 [doi]
- FPGA-Based Acceleration of Block Matching Motion Estimation TechniquesDiego González, Guillermo Botella Juan, Soumak Mokheerje, Uwe Meyer-Bäse. 389-392 [doi]
- An Optimized FPGA Implementation of the Modified Space Vector Modulation Algorithm for AC Drives ControlBogdan Alecsa, Alexandru Onea. 393-395 [doi]
- Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor NodeFrançois Philipp, Manfred Glesner. 396-398 [doi]
- Real-Time Evaluation of Remote Sensing Data on Board of SatellitesKurt Schwenk, Katharina Goetz, Maria von Schoenermark, Felix Huber. 399-400 [doi]
- Heterogeneous Platform for Stream Based Applications on FPGAsJan Kloub, Tomas Mazanec, Antonin Hermanek. 401-404 [doi]
- Implementation in FPGA of Address-Based Data SortingValery Sklyarov, Iouliia Skliarova, Dmitri Mihhailov, Alexander Sudnitson. 405-410 [doi]
- Novel and Highly Efficient Reconfigurable Implementation of Data Mining Classification TreeGrigorios Chrysos, Panagiotis Dagritzikos, Ioannis Papaefstathiou, Apostolos Dollas. 411-416 [doi]
- FPGA Acceleration of the Phylogenetic Parsimony Kernel?Nikolaos Alachiotis, Alexandros Stamatakis. 417-422 [doi]
- Timing-Driven Routing of High Fanout NetsXun Chen, Jianwen Zhu, Minxuan Zhang. 423-428 [doi]
- Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCsStefan Wildermann, Jürgen Teich, Daniel Ziener. 429-434 [doi]
- Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB CodesignSeong-I. Lei, Wai-Kei Mak. 435-440 [doi]
- A Radiation Hard Lut Block with Auto-ScrubbingKashfia Haque, Paul Beckett. 441-446 [doi]
- FPGA Interconnect Architecture Exploration Based on a Statistical ModelZhen Wang, Ding Xie, Jinmei Lai. 447-452 [doi]
- Capacitive Boosting for FPGA Interconnection NetworksFatemeh Eslami, Mihai Sima. 453-458 [doi]
- Scalable FRM-SSA SoC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real TimeOrsalia Georgia Hazapis, Elias S. Manolakos. 459-463 [doi]
- Synthesizing Tiled Matrix Decomposition on FPGAsYi-Gang Tai, Kleanthis Psarris, Chia-Tien Dan Lo. 464-469 [doi]
- Acceleration of Multi-agent Simulation on FPGAsLintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He. 470-473 [doi]
- Molecular Docking on FPGA and GPU PlatformsImre Pechan, Béla Féher. 474-477 [doi]
- Pattern Compression of FAST Corner Detection for Efficient Hardware ImplementationKeisuke Dohi, Yuji Yorita, Yuichiro Shibata, Kiyoshi Oguri. 478-481 [doi]
- IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAsZhe Feng, Naifeng Jing, Gengsheng Chen, Yu Hu, Lei He. 482-485 [doi]
- Resource Management for the Heterogeneous Arrays of Hardware AcceleratorsZdenek Pohl, Milan Tichý. 486-489 [doi]
- A Coarse Grain Reconfigurable Processor Architecture for Stream Processing EngineTakefumi Miyoshi, Hideyuki Kawashima, Yuta Terada, Tsutomu Yoshinaga. 490-495 [doi]
- Remote FPGA Lab with Interactive Control and Visualisation InterfaceFearghal Morgan, Seamus Cawley, Frank Callaly, Shane Agnew, Patrick Rocke, Martin O'Halloran, Nina Drozd, Krzysztof Kepa, Brian McGinley. 496-499 [doi]
- Cryptographic Extension for Soft General-Purpose Processors with Secure Key ManagementLubos Gaspar, Viktor Fischer, Lilian Bossuet, Milos Drutarovský. 500-505 [doi]
- Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAsRajesh Velegalati, Jens-Peter Kaps. 506-511 [doi]
- Compact CLEFIA Implementation on FPGASPaulo Proenca, Ricardo Chaves. 512-517 [doi]
- Improved Abstractions and Turnaround Time for FPGA Design Validation and DebugYousef Iskander, Cameron D. Patterson, Stephen D. Craven. 518-523 [doi]
- Speculative Debug Insertion for FPGAsEddie Hung, Steven J. E. Wilton. 524-531 [doi]
- Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA SystemsCristiana Bolchini, Antonio Miele, Chiara Sandionigi. 532-538 [doi]
- On Timing Yield Improvement for FPGA Designs Using Architectural SymmetryHaile Yu, Qiang Xu, Philip Heng Wai Leong. 539-544 [doi]
- Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless NetworkingXinyu Niu, Kuen Hung Tsoi, Wayne Luk. 545-550 [doi]
- Optimizing an Open-Source Processor for FPGAs: A Case StudyLyonel Barthe, Luis Vitório Cargnini, Pascal Benoit, Lionel Torres. 551-556 [doi]