An FPGA Solver for SAT-Encoded Formal Verification Problems

Kenji Kanazawa, Tsutomu Maruyama. An FPGA Solver for SAT-Encoded Formal Verification Problems. In International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece. pages 38-43, IEEE, 2011. [doi]

Abstract

Abstract is missing.