- Chaofei Yang, Ximing Qiao, Yiran Chen. Neuromorphic Computing Systems: From CMOS To Emerging Nonvolatile Memory. IPSJ T. on System LSI Design Methodology, 12:53-64, 2019.
- Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi. Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses. IPSJ T. on System LSI Design Methodology, 12:78-80, 2019.
- Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama. Communication-Aware Scheduling of Data-Parallel Tasks on Multicore Architectures. IPSJ T. on System LSI Design Methodology, 12:65-73, 2019.
- Seiya Shirakuni, Ittetsu Taniguchi, Hiroyuki Tomiyama. Design and Evaluation of Asymmetric and Symmetric 32-core Architectures on FPGA. IPSJ T. on System LSI Design Methodology, 12:42-45, 2019.
- Hiroki Koyasu, Yasuhiro Takahashi. Current Pass Optimized Symmetric Pass Gate Adiabatic Logic for Cryptographic Circuits. IPSJ T. on System LSI Design Methodology, 12:50-52, 2019.
- Yang Liu 0001, Lin Meng, Hiroyuki Tomiyama. A Genetic Algorithm for Scheduling of Data-parallel Tasks on Multicore Architectures. IPSJ T. on System LSI Design Methodology, 12:74-77, 2019.
- Nozomu Togawa. Message from the Editor-in-Chief. IPSJ T. on System LSI Design Methodology, 12:1, 2019.
- Kenshu Seto. Scalar Replacement with Circular Buffers. IPSJ T. on System LSI Design Methodology, 12:13-21, 2019.
- Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa. An FPGA Implementation Method based on Distributed-register Architectures. IPSJ T. on System LSI Design Methodology, 12:38-41, 2019.
- Salita Sombatsiri, Seiya Shibata, Yuki Kobayashi, Hiroaki Inoue, Takashi Takenaka, Takeo Hosomi, Jaehoon Yu, Yoshinori Takeuchi. Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA. IPSJ T. on System LSI Design Methodology, 12:22-37, 2019.