Abstract is missing.
- Path breaker: a tool for the optimal design of speed independent asynchronous controllersYogesh Mishra, Sunil D. Sherlekar, G. Venkatesh. 2-8 [doi]
- Asynchronous state machine synthesis using data driven clocksFarhad Aghadasi. 9-14 [doi]
- Design of delay insensitive circuits using multi-ring structuresJens Sparsø, Jørgen Staunstrup, Michael Dantzer-Sørensen. 15-20 [doi]
- DESB, a functional abstractor for CMOS VLSI circuitsM. Laurentin, Alain Greiner, Roland Marbot. 22-27 [doi]
- Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulationRonald B. Stewart, Véronique Anjubault, Philippe Garcin, Jacques Benkoski. 28-31 [doi]
- Communication based logic partitioningMark Beardslee, Bill Lin, Alberto L. Sangiovanni-Vincentelli. 32-37 [doi]
- Parallel algorithms for slicing based final placementHenning Spruth, Georg Sigl. 40-45 [doi]
- Wolverines: standard cell placement on a network of workstationsSundarar Mohan, Pinaki Mazumder. 46-51 [doi]
- A genetic algorithm for macro cell placementHenrik Esbensen. 52-57 [doi]
- Timing models for high-level synthesisViraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski. 60-65 [doi]
- System clock estimation based on clock slack minimizationSanjiv Narayan, Daniel D. Gajski. 66-71 [doi]
- Combined topological and functionality based delay estimation using a layout-driven approach for high level applicationsChampaka Ramachandran, Fadi J. Kurdahi. 72-78 [doi]
- Correctness verification of concurrent controller specificationsM. T. L. Schaefer, W. U. Klein. 80-85 [doi]
- Design verification considering manufacturing tolerances by using worst-caste distancesHelmut E. Graeb, Claudia U. Wieser, Kurt Antreich. 86-91 [doi]
- State machine abstraction from circuit layouts using BDD's: applications in verification and synthesisTimothy Kam, P. A. Subrahmanyam. 92-97 [doi]
- Verification of digital circuits based on formal semantics of a hardware description languageMatthias Mutz. 98-103 [doi]
- An integer programming approach to instruction implementation method selection problemMasaharu Imai, Jun Sato, Alauddin Alomary, Nobuyuki Hikichi. 106-111 [doi]
- Flexible controlpath microarchitecture synthesis based on artificial intelligenceA. J. W. M. ten Berg. 112-117 [doi]
- Performance-driven interconnection optimization for microarchitecture synthesisYi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin. 118-123 [doi]
- Transient simulation of lossy coupled transmission linesShen Lin, Ernest S. Kuh. 126-131 [doi]
- The exact solution of timing verificationEdgar Bolender, Hans Martin Lipp. 132-137 [doi]
- DynaTAPP: dynamic timing analysis with partial path activation in sequential circuitsPrathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth. 138-141 [doi]
- Delay macromodels for the timing analysis of GaAs DCFLAyman I. Kayssi, Karem A. Sakallah. 142-145 [doi]
- An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraintsEric Felt, Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli. 148-153 [doi]
- PERFLEX: a performance driven module generatorSoohong Kim, Robert Michael Owens, Mary Jane Irwin. 154-159 [doi]
- P.SIZE: a sizing aid for optimized designsNadine Azémard, V. Bonzom, Daniel Auvergne. 160-165 [doi]
- Boolean matching in logic synthesisHamid Savoj, Mário J. Silva, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 168-174 [doi]
- ALU synthesis from HDL descriptions to optimized multi-level logicFrank Buijs. 175-180 [doi]
- Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functionsBogdan J. Falkowski, Ingo Schäfer, Marek A. Perkowski. 181-186 [doi]
- High-level synthesis in a rapid-prototype environment for mechatronic systemsNorbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner. 188-193 [doi]
- Application-specific microelectronics for mechatronic systemsPeter Windirsch, Hans-Jürgen Herpel, A. Laudenbach, Manfred Glesner. 194-199 [doi]
- On the intrinsic rent parameter and spectra-based partitioning methodologiesLars W. Hagen, Fadi J. Kurdahi, Champaka Ramachandran, Andrew B. Kahng. 202-208 [doi]
- Embedded pin assignment for top down system designThomas Pförtner, Stefan Kiefl, Reimund Dachauer. 209-214 [doi]
- Chip assembly in the PLAYOUT VLSI design systemKlaus Glasmacher, Gerhard Zimmermann. 215-221 [doi]
- Maximal reduction of lookup-table based FPGAsKuang-Chien Chen, Jason Cong. 224-229 [doi]
- A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mappingWei Wan, Marek A. Perkowski. 230-235 [doi]
- Towards a requirements definition, specification and system design environmentKlaus D. Müller-Glaser, Jürgen Bortolazzi, Yankin Tanurhan. 238-243 [doi]
- SIESTA: a multi-facet scan design systemSridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer. 246-251 [doi]
- Tackling cost optimization in testable design by forward inferencingMichiel Kraak, Ralph H. J. M. Otten. 252-257 [doi]
- A multi level testability assistant for VLSI designMassimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Donatella Sciuto, Giuseppe Zaza. 258-263 [doi]
- Efficient constrained encoding for VLSI sequential logic synthesisC.-J. Richard Shi, Janusz A. Brzozowski. 266-271 [doi]
- ROM-based finite state machines with PLA address modifiersTadeusz Luba, K. Górski, Leszek B. Wronski. 272-277 [doi]
- Minimal area merger of finite state machine controllersDebaditya Mukherjee, Massoud Pedram, Melvin A. Breuer. 278-283 [doi]
- Routing algorithms for multi-chip modulesJens Lienig, Krishnaiyan Thulasiraman, M. N. S. Swamy. 286-291 [doi]
- A fast multilayer general area router for MCM designsKei-Yong Khoo, Jason Cong. 292-297 [doi]
- A distributed routing system for multilayer SOGTakashi Shimamoto, Hidetaka Hane, Isao Shirakawa, Shuji Tsukiyama, Shoji Shinoda, Nobuyasu Yui, Nobuyuki Nishiguchi. 298-303 [doi]
- Cross-fertilizing FSM verification techniques and sequential diagnosisGianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 306-311 [doi]
- Generation of deterministic test patterns by minimal basic test setsArno Kunzmann. 312-317 [doi]
- MILEF: an efficient approach to mixed level automatic test pattern generationUwe Gläser, Heinrich Theodor Vierhaus. 318-321 [doi]
- Automatic partitioning for deterministic testDidier Crestani, A. Aguila, M.-H. Gentil, P. Chardon, C. Durante. 322-325 [doi]
- Automatic module allocation in high level synthesisPeter Gutberlet, Jens Müller, Heinrich Krämer, Wolfgang Rosenstiel. 328-333 [doi]
- Heuristics for branch-and-bound global allocationJulio Septién, Daniel Mozos, Francisco Tirado, Román Hermida, Milagros Fernández. 334-340 [doi]
- A neural network based algorithm for the scheduling problem in high-level synthesisMehrdad Nourani, Christos A. Papachristou, Yoshiyasu Takefuji. 341-346 [doi]
- An optimal channel pin assignment with multiple intervals for building block layoutTetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida. 348-353 [doi]
- Crossing distributionDeborah C. Wang, C. Bernard Shung. 354-361 [doi]
- A performance driven generator for efficient testable conditional-sum-addersBernd Becker, Paul Molitor. 370-375 [doi]
- A time optimal robust path-delay-fault self-testable adderBernd Becker, Rolf Drechsler. 376-381 [doi]
- Design for testability view on placement and routingDerek Feltham, Jitendra Khare, Wojciech Maly. 382-387 [doi]
- Generating pipelined datapaths using reduction techniques to shorten critical pathsDonald A. Lobo, Barry M. Pangrle. 390-395 [doi]
- Harmonic scheduling of linear recurrences for digital filter designHaigeng Wang, Nikil Dutt, Alexandru Nicolau. 396-401 [doi]
- SYNTEST: an environment for system-level design for testHaidar Harmanani, Christos A. Papachristou, Scott Chiu, Mehrdad Nourani. 402-407 [doi]
- A fast and accurate characterization method for full-CMOS circuitsRafael Peset Llopis, Hans G. Kerkhoff. 410-415 [doi]
- An exact analytic technique for simulating uniform RC linesJaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson. 416-420 [doi]
- A dynamic scheduling algorithm for the simulation of MOS and bipolar circuits using waveform relaxationWerner Rissiek, Werner John. 421-426 [doi]
- SPADES: a simulator for path delay faults in sequential circuitsIrith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy. 428-435 [doi]
- Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-upBernd Becker, Ralf Hahn, Rolf Krieger. 436-441 [doi]
- Linear time fault simulation algorithm using a content addressable memoryNagisa Ishiura, Shuzo Yajima. 442-445 [doi]
- SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalenceChing Ping Wu, Chung-Len Lee, Wen-Zen Shen. 446-449 [doi]
- On modeling integrated design environmentsChristoph Hübel, Detlev Ruland, Ernst Siepmann. 452-458 [doi]
- Information modelling of folded and unfolded designGerhard Scholz, Wolfgang Wilkes. 459-464 [doi]
- Locating logic design errors via test generation and don't-care propagationSy-Yen Kuo. 466-471 [doi]
- New design error modeling and metrics for design validationSungho Kang, Stephen A. Szygenda. 472-477 [doi]
- Random current testing for CMOS logic circuits by monitoring a dynamic power supply currentHideo Tamamoto, Hiroshi Yokoyama, Yuichi Narita. 480-485 [doi]
- Test generation for IDDQ testing and leakage fault detection in CMOS circuitsUdo Mahlstedt, Matthias Heinitz, Jürgen Alt. 486-491 [doi]
- Design assistance for CAD frameworksJuan Carlos López, Margarida F. Jacome, Stephen W. Director. 494-499 [doi]
- Unifying tool, data and process flow managementMichael Rumsey, Colin Farquhar. 500-505 [doi]
- ANT - a test harness for the NELSIS CAD systemC. A. Schot, Mattie N. Sim, Peter M. Kist. 506-511 [doi]
- Finite state machine verification on MIMD machinesNand Kumar, Ranga Vemuri. 514-520 [doi]
- An approach to multi-paradigm controller synthesis from timing diagram specificationsWolf-Dieter Tiedemann. 522-527 [doi]
- Cellular scan test generation for sequential circuitsClay S. Gloster Jr., Franc Brglez. 530-536 [doi]
- Experiments on the synthesis and testability of non-scan finite state machinesMichael Pabst, Tiziano Villa, A. Richard Newton. 537-542 [doi]
- A quantitative measure of robustness for delay fault testingWeiwei Mao, Michael D. Ciletti. 543-549 [doi]
- JESSI COMMON FRAMEWORK Design Management: the means to configuration and execution of the design processDaniel C. Liebisch, Adidev Jain. 552-557 [doi]
- Design of a tool interface for integrated CAD-environmentsUwe Hunzelmann, Wolfgang Wilkes, Gunter Schlageter. 558-563 [doi]
- Representing the hardware design process by a common data schemaMaria Brielmann, Elisabeth Kupitz. 564-569 [doi]
- GOSSIP: a generic system for statistical circuit designLeszek J. Opalski, M. A. Styblinski. 572-577 [doi]
- A generic software system for drift reliability optimization of VLSI circuitsMin Huang, M. A. Styblinski. 578-583 [doi]
- PAR-APLAC: Parallel Circuit Analysis and OptimizationEero Pajarre, Tapani Ritoniemi, T. Tenhunen. 584-589 [doi]
- Design technology research for the nineties: more of the same?Hugo De Man. 592-596 [doi]
- Challenges for CAD in computer development in the 1990sGünter Dedié. 597-598 [doi]
- Electronic System Design: tools and methodology to meet the productivity challengeRoy Davies. 599-600 [doi]
- Compiling VHDL into a high-level synthesis design representationPetru Eles, Krzysztof Kuchcinski, Zebo Peng, Marius Minea. 604-609 [doi]
- Flexible timing specification in a VHDL synthesis subsetA. Stoll, J. Biesenack, S. Rumler. 610-615 [doi]
- Semantics and synthesis of signals in behavioral VHDLLoganath Ramachandran, Frank Vahid, Sanjiv Narayan, Daniel D. Gajski. 616-621 [doi]
- Integration of SDL and VHDL for high-level digital designO. Pulkkinen, Klaus Kronlöf. 624-629 [doi]
- Using VHDL for simulation of SDL specificationsB. Lutter, Wolfgang Glunz, Franz-Josef Rammig. 630-635 [doi]
- VHDL and fuzzy logic if-then rulesAlex N. D. Zamfirescu, Cary Ussery. 636-641 [doi]
- Experiences and issues in VHDL-based synthesisStephen E. Lim, David C. Hendry, Ping F. Yeung. 646-651 [doi]
- VHDL for high speed desktop video ICs: experience with replacement of other simulatorMichael Jacobsen, Wolfgang Nebel. 652-657 [doi]
- Design of complex systems with a VHDL based methodologyS. Amadori, P. Coerezza. 658-663 [doi]
- 1992 VHDL standardization overviewMoe Shahdad. 666-667 [doi]
- Analysis of user requirementsJacques Rouillard. 668-671 [doi]
- VHDL 1076-1992 languages changesAndrew Guyler. 672-678 [doi]
- Synchronous design in VHDLAlain Debreil, Philippe Oddo. 680-681 [doi]
- Towards a common RT-level subset of VHDLWolfgang Ecker. 682 [doi]
- Selected aspects of component modelingAdam Pawlak. 683 [doi]
- Interest of a VHDL native environmentJ. L. Giordana. 684-685 [doi]
- Multi-kernel simulation description within VHDLChristel Oczko, Michael W. Nitsche. 686 [doi]
- VHDL intermediate format standardization activity: status and trendsAlain Fonkoua, Jacques Rouillard. 687-688 [doi]
- Temporal verification of behavioral descriptions in VHDLDjamel Boussebha, Norbert Giambiasi, Janine Magnier. 692-697 [doi]
- Providing a VHDL-interface for proof systemsGabriele Umbreit. 698-703 [doi]
- Towards a standard VHDL synthesis packagePaul L. Harper, Ken Scott. 706-712 [doi]
- VHDL analog extensions: process, issues and statusRobert A. Cottrell, Kevin Nolan, Mark Brown. 713-717 [doi]
- Subtype concept of VHDL for synthesis constraintsWolfgang Ecker, Sabine März. 720-725 [doi]
- Synthesis of VHDL arrays on RAM cellsChristian Berthet, Jérôme Rampon, L. Sponga. 726-731 [doi]
- Using VHDL for datapath synthesisVincent Olive, R. Airiau, J. M. Bergé, Anne Robert. 732-737 [doi]
- Challenges in the analysis of VHDLDavid B. Bernstein, Rodney Farrow, David Charness. 740-745 [doi]
- Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & MSerge Maginot. 746-751 [doi]
- The design cube: a new model for VHDL designflow representationWolfgang Ecker, M. Hofmeister. 752-757 [doi]
- VHDL intermediate form standardization: process, issues and statusMark Brown. 758-762 [doi]