G. Venkatesh - researchr alias

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Viewing Publication 1 - 35 from 35

2019

Map Reduce for big data processing based on traffic aware partition and aggregationG. Venkatesh, K. Arunesh. cluster, 22(5):12909-12915, 2019. [doi]

2014

Message from steering committeeUday Desai, Giridhar Mandyam, Rajeev Shorey, G. Venkatesh. comsnets 2014: 1-2 [doi]

Mobile-First Strategy for MSMEs in Emerging MarketsG. Venkatesh, V. Sridhar. itpro, 16(1):58-61, 2014. [doi]

2011

Temporal Logic with Preferences and Reasoning About GamesG. Venkatesh. In Johan van Benthem, Amitabha Gupta, Rohit Parikh, editors, Proof, Computation and Agency - Logic at the Crossroads. Volume 352 of Synthese library, pages 241-258, Springer, 2011. [doi]

2010

CDPN: Communicating Dynamic Petri Net for Adaptive Multimedia PresentationA. P. Sarath Chandar, S. Arun Balaji, G. Venkatesh, Susan Elias. ICT 2010: 165-170 [doi]

2004

Reasoning About Game Equilibria Using Temporal LogicG. Venkatesh. fsttcs 2004: 506-517 [doi]

1998

1997

Proof of Correctness of a Direct Construction of DFA from Regular ExpressionS. Ramesh Babu, Amitabha Sanyal, G. Venkatesh. ijcm, 64(3-4):191-210, 1997. [doi]

Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR FiltersMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. vlsid 1997: 124-129 [doi]

1996

1995

Labeled Lambda-Calculus and a Generalized Notion of Strictness (An Extended Abstract)Milind Gandhe, G. Venkatesh, Amitabha Sanyal. asian 1995: 103-110

A new methodology for the design of low-cost fail safe circuits and networksB. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh. vlsid 1995: 355-358 [doi]

Synthesis of multiplier-less FIR filters with minimum number of additionsMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. iccad 1995: 668-671 [doi]

Techniques for low power realization for FIR filtersMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. aspdac 1995: [doi]

Concurrent Error Detection Using Monitoring MachinesRubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. dt, 12(3):24-32, 1995. [doi]

An Automaton-Driven Frame Disposal Algorithm and its Proof of CorrectnessManoranjan Satpathy, Amitabha Sanyal, G. Venkatesh. asian 1995: 88-102

1993

A Propositional Dense Time Logic (Based on Nested Sequences)Mohsin Ahmed, G. Venkatesh. tapsoft 1993: 584-598

State Assignment for Optimal Design of Monitored Self-Checking Sequential CircuitsRubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. vlsid 1993: 15-20

1992

A Behavioral Fault Simulator for IdealAjay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran. dt, 9(4):14-21, 1992. [doi]

A Behavioral Fault Simulator For IdealAjay Khoche, Sunil D. Sherlekar, G. Venkatesh. vlsid 1992: 137-143 [doi]

Path breaker: a tool for the optimal design of speed independent asynchronous controllersYogesh Mishra, Sunil D. Sherlekar, G. Venkatesh. eurodac 1992: 2-8 [doi]

1991

A methodology for the design of SFS/SCD circuits for a class of unordered codesSandeep Pagey, Sunil D. Sherlekar, G. Venkatesh. et, 2(3):261-277, 1991. [doi]

A Methodology for Designing Optimal Self-Checking Sequential CircuitsRubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar. itc 1991: 283-291

1989

Improving Prolog Performance by Inductive Proof GeneralizationsMilind Gandhe, G. Venkatesh. kbcs 1990: 243-253

1986

Reasoning about digital systems using temporal logicS. Bapat, G. Venkatesh. dac 1986: 215-219 [doi]

1985

A Decision Method for Temporal Logic Based on ResolutionG. Venkatesh. fsttcs 1985: 272-289

1982

Window Random Access Protocols for Local Computer NetworksDonald F. Towsley, G. Venkatesh. TC, 31(8):715-722, 1982.

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