Table of Contents

• Optimal algorithms for planar over-the-cell routing in the presence of obstaclesSrinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani. 3-7 [doi]
• A fast algorithm to test planar topological routabilityAndrew Lim, Sartaj K. Sahni, Venkat Thanvantri. 8-12 [doi]
• Parallel algorithms for single row routing in narrow streetsS. Das, Sanjeev Saxena. 13-18 [doi]
• A consistent labeling approach to hardware software partitioningRaj S. Mitra, Mahmood G. Qadir, Anupam Basu. 19-24 [doi]
• Object oriented data modeling for VLSI/CADAnoop Singhal, Chi-Yuan Lo. 25-29 [doi]
• Implementation of design functions by available devices: a new algorithmRaj S. Mitra, Partha S. Roop, Anupam Basu. 30-35 [doi]
• An asynchronous algorithm for sequential circuit test generation on a network of workstationsJames Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal. 36-41 [doi]
• Robust testing for stuck-at faultsTapan J. Chakraborty, Vishwani D. Agrawal. 42-46 [doi]
• Functional test generation for non-scan sequential circuitsMandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal. 47-52 [doi]
• A fast-multiplier generator for FPGAsSuthikshn Kumar, Kevin E. Forward, M. Palaniswami. 53-56 [doi]
• Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architectureSantanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri. 57-62 [doi]
• Synthesis of multiplexer network using ratio parameters and mapping onto FPGAsA. Pal, R. K. Gorai, V. V. S. S. Raju. 63-68 [doi]
• AATMA: an algorithm for technology mapping for antifuse-based FPGAsMahesh Mehendale, M. K. Ram Prasad. 69-74 [doi]
• Heuristic search based approach to scheduling, allocation and binding in Data Path SynthesisAlok Kumar, Anshul Kumar, M. Balakrishnan. 75-80 [doi]
• Efficient variable ordering and partial representation algorithmJawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross. 81-86 [doi]
• Synchronization of communicating modules and processes in high level synthesisSantonu Sarkar, Anupam Basu, Arun K. Majumdar. 87-92 [doi]
• Functional clock schedule optimizationAlexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 93-98 [doi]
• Generation of search state equivalence for automatic test pattern generationXinghao Chen, Michael L. Bushnell. 99-103 [doi]
• Test generation for cyclic combinational circuitsAnand Raghunathan, Pranav Ashar, Sharad Malik. 104-109 [doi]
• MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer LevelSitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy. 110-115 [doi]
• Parallel test generation with low communication overheadS. Venkatraman, Sharad C. Seth, Prathima Agrawal. 116-120 [doi]
• PLA based synthesis and testing of hazard free logicU. K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta. 121-124 [doi]
• A new switching-level approach to multiple-output functions synthesisCristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli. 125-129 [doi]
• Retiming of synchronous circuits with variable topologySven Simon, Ralf Bucher, Josef A. Nossek. 130-134 [doi]
• Optimum retiming of large sequential circuitsSrimat T. Chakradhar. 135-140 [doi]
• Fully asynchronous, robust, high-throughput arithmetic structuresPriyadarsan Patra, Donald S. Fussell. 141-145 [doi]
• SAGA: the first general-purpose on-line arithmetic co-processorAli Skaf, Alain Guyot. 146-149 [doi]
• A single chip, pipelined, cascadable, multichannel, signal processorS. Krishnakumar, P. Suresh, S. Sadashiva Rao, M. P. Pareek, R. Gupta. 150-155 [doi]
• VLSI design of systematic odd-weight-column byte error detecting SEC-DED codesLuca Penzo, Donatella Sciuto, Cristina Silvano. 156-160 [doi]
• An efficient automatic test generation system for path delay faults in combinational circuitsAnanta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal. 161-165 [doi]
• Statistical methods for delay fault coverage analysisKeerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell. 166-170 [doi]
• Synthesis of asynchronous circuits for stuck-at and robust path delay fault testabilitySteven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng. 171-176 [doi]
• A graph approach to DFT hardware placement for robust delay fault BISTImtiaz P. Shaik, Michael L. Bushnell. 177-182 [doi]
• A highly testable ASIC for telephone signalingP. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar. 183 [doi]
• Wave pipelined architecture folding: a method to achieve low power and low areaDebabrata Ghosh, Soumitra Kumar Nandy. 184 [doi]
• The Pentium processor-90/100, microarchitecture and low power circuit designGoutam Debnath, K. Debnath, R. Fernando. 185-190 [doi]
• Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded arrayPuneet Sawhney, Haroon Rasheed. 191 [doi]
• A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 /spl mu/m CMOS technologyVarna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh. 192 [doi]
• CODAC-a characterization system for digital and analog circuitsNagaraj Subramanyam, K. G. Praveen, Ramesh Ramani, D. Suryanarayana. 193 [doi]
• CVD-diamond substrates for multi-chip modules (MCMs)Hameed A. Naseem, Ajay P. Malshe, Rajan A. Beera, M. Shahid Haque, William D. Brown, Len W. Schaper. 194 [doi]
• Computing area and wire length efficient routes for channelsRajat K. Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal. 196-201 [doi]
• A general graph theoretic framework for multi-layer channel routingRajat K. Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal. 202-207 [doi]
• Testability-oriented channel routingJitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar. 208-213 [doi]
• VLSI implementation of variable resolution image compressionHossein Sahabi, Anup Basu, Mark Fiala. 214-219 [doi]
• JAGUAR: a high speed VLSI chip for JPEG image compression standardMario Kovac, N. Ranganathan. 220-224 [doi]
• Logic minimization based approach for compressing image dataJacob Augustine, Wen Feng, James Jacob. 225-228 [doi]
• Efficient simulation of interconnect and mixed analog-digital circuits in ACESAnirudh Devgan, Ronald A. Rohrer. 229-233 [doi]
• Efficient multisine testing of analog circuitsNaveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham. 234-238 [doi]
• Exposing floating gate defects in analogue CMOS circuits by power supply voltage control testing techniqueA. K. B. A ain, A. H. Bratt, A. P. Dorey. 239-242 [doi]
• Transformations for functional verification of synthesized designsWilliam L. Bradley, Ranga Vemuri. 243-248 [doi]
• An HOL based framework for design of correct high level synthesizersB. M. Subraya, Anshul Kumar, Shashi Kumar. 249-254 [doi]
• Formal synthesis of circuits with a simple handshake protocolRamayya Kumar, Thomas Kropf, Klaus Schneider. 255-259 [doi]
• Transmission line model parameters for very high speed VLSI interconnects in MCMs using FEM with special elementsS. Y. Kulkarni, K. D. Patil, K. V. V. Murthy. 260-263 [doi]
• EM simulation [ICs and MCMs]D. V. Das. 264-267 [doi]
• Analysis of temperature dependence of Si-Ge HBTG. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee. 268-271 [doi]
• HISCOAP: a hierarchical testability analysis toolC. P. Ravikumar, Hemant Joshi. 272-277 [doi]
• A C-testable modified Booth s array multiplierS. M. Aziz. 278-282 [doi]
• Partial scan design for technology mapped circuitsArun Balakrishnan, Srimat T. Chakradhar. 283-287 [doi]
• A genetic approach to test application time reduction for full scan and partial scan circuitsElizabeth M. Rudnick, Janak H. Patel. 288-293 [doi]
• Minimizing power consumption of static CMOS circuits by transistor sizing and input reorderingManjit Borah, Mary Jane Irwin, Robert Michael Owens. 294-298 [doi]
• Analog gates for a VLSI fuzzy processorVincenzo Catania, Marco Russo. 299-304 [doi]
• Circuit optimization for minimisation of power consumption under delay constraintS. C. Prasad, Kaushik Roy. 305-309 [doi]
• A novel CMOS monolithic analog multiplier with wide input dynamic rangeGeorge A. Hadgis, P. R. Mukund. 310-314 [doi]
• Design of a VLSI parallel processor for fuzzy computingGiuseppe Ascia, Vincenzo Catania. 315-320 [doi]
• Design of a highly reconfigurable interconnect for array processorsLizy Kurian John, Daniel Brewer, Eugene John. 321-325 [doi]
• A VLSI architecture for the computation of NURBS patchesMeenakshisundaram Gopi, Swami Manohar. 326-331 [doi]
• A modular systolic architecture for delayed least mean squares adaptive filteringV. Visvanathan, S. Ramanathan. 332-337 [doi]
• Voting model based diagnosis of bridging faults in combinational circuitsSreejit Chakravarty, Yiming Gong. 338-342 [doi]
• Board level fault diagnosis using cellular automata arraySantanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri. 343-348 [doi]
• An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processorsYung-Yuan Chen, Ching-Hwa Cheng, Jwu-E Chen. 349-354 [doi]
• A new methodology for the design of low-cost fail safe circuits and networksB. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh. 355-358 [doi]
• A new fuzzy-clustering-based approach for two-way circuit partitioningJin-Tai Yan, Pei-Yung Hsiao. 359-364 [doi]
• Genetic multiway partitioningKhushro Shahookar, Pinaki Mazumder. 365-369 [doi]
• VLSI floorplan generation and area optimization using AND-OR graph searchP. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya. 370-375 [doi]
• Resource requirements for field programmable interconnection chipsDinesh Bhatia, James Haralambides. 376-380 [doi]
• Svoboda-Tung division with no compensationLuis A. Montalvo, Alain Guyot. 381-385 [doi]
• Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividersAlain Guyot, Luis A. Montalvo, A. Houelle, Habib Mehrez, N. Vaucher. 386-391 [doi]
• Design of a 3-bit Booth recoded novel VLSI concurrent multiplier-accumulator architectureD. V. Poornaiah, P. V. Ananda Mohan. 392-397 [doi]
• A 16-bit x 16-bit 1.2 /spl mu/ CMOS multiplier with low latency vector mergingW. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi. 398-402 [doi]
• An improved output compaction technique for built-in self-test in VLSI circuitsSunil R. Das, H. T. Ho, Wen-Ben Jone, A. R. Nayak. 403-407 [doi]
• Combined optimization of area and testability during state assignment of PLA-based FSM sChunduri Rama Mohan, Partha Pratim Chakrabarti. 408-413 [doi]
• Fast computation of MISR signaturesManoj Franklin, Kewal K. Saluja, Kyuchull Kim. 414-418 [doi]
• A differential built-in current sensor design for high speed IDDQ testingJason P. Hurst, Adit D. Singh. 419-423 [doi]