Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy. MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. In 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India. pages 110-115, IEEE Computer Society, 1995. [doi]
Abstract is missing.