Pranav Ashar - researchr alias

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Viewing Publication 1 - 70 from 70

2019

Closing the Verification Gap with Static Sign-offPranav Ashar, Vinod Viswanath. isqed 2019: 343-347 [doi]

2017

Failures and verification solutions related to untimed paths in SOCsPranav Ashar, Vikas Sachdeva, Vinod Viswanath. isqed 2017: 460-465 [doi]

2016

A paradigm shift in verification methodologyPranav Ashar. FMCAD 2016: 6 [doi]

2013

Static verification based signoff - A key enabler for managing verification complexity in the modern socPranav Ashar. FMCAD 2013: 15 [doi]

2010

Clock domain verification challenges and scalable solutionsPranav Ashar. hldvt 2010: 66 [doi]

2008

Efficient SAT-based bounded model checking for software verificationFranjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar. TCS, 404(3):256-274, 2008. [doi]

Bitwidth Reduction via Symbolic Interval Analysis for Software Model CheckingAleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar. tcad, 27(8):1513-1517, 2008. [doi]

2006

Efficient distributed SAT and SAT-based distributed Bounded Model CheckingMalay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar. STTT, 8(4-5):387-396, 2006. [doi]

Panel: Assertion-Based Verification -What's the Big Deal?Sandeep K. Shukla, Alan J. Hu, Jacob Abrahams, Pranav Ashar, Harry Foster, Avner Landver, Carl Pixley. hldvt 2006: 183 [doi]

2005

2004

Efficient SAT-based Bounded Model Checking for Software VerificationPranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang. ISoLA 2004: 157-164

Efficient Modeling of Embedded Memories in Bounded Model CheckingMalay K. Ganai, Aarti Gupta, Pranav Ashar. cav 2004: 440-452 [doi]

Efficient SAT-based unbounded symbolic model checking using circuit cofactoringMalay K. Ganai, Aarti Gupta, Pranav Ashar. iccad 2004: 510-517 [doi]

2003

2002

2001

2000

1999

1998

Verification of RTL generated from scheduled behavior in a high-level synthesis flowPranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, Akira Mukaiyama. iccad 1998: 517-524 [doi]

Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence CheckingAarti Gupta, Pranav Ashar. vlsid 1998: 222-225 [doi]

Guarded evaluation: pushing power management to logic synthesis/designVivek Tiwari, Sharad Malik, Pranav Ashar. tcad, 17(10):1051-1060, 1998. [doi]

Solving Boolean Satisfiability with Dynamic Hardware ConfigurationsPeixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik. fpl 1998: 326-335 [doi]

Accelerating Boolean Satisfiability with Configurable HardwarePeixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik. fccm 1998: 186-195 [doi]

Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean SatisfiabilityPeixin Zhong, Pranav Ashar, Sharad Malik, Margaret Martonosi. dac 1998: 194-199 [doi]

1997

Toward Formalizing a Validation Methodology Using Simulation CoverageAarti Gupta, Sharad Malik, Pranav Ashar. dac 1997: 740-745 [doi]

1996

Using complete-1-distinguishability for FSM equivalence checkingPranav Ashar, Aarti Gupta, Sharad Malik. iccad 1996: 346-353 [doi]

Scheduling Techniques to Enable Power ManagementJosé Monteiro, Srinivas Devadas, Pranav Ashar, Ashutosh Mauskar. dac 1996: 349-352 [doi]

Technology mapping for low power in logic synthesisVivek Tiwari, Pranav Ashar, Sharad Malik. integration, 20(3):243-268, 1996. [doi]

1995

1994

Efficient breadth-first manipulation of binary decision diagramsPranav Ashar, Matthew Cheong. iccad 1994: 622-627 [doi]

Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other ApplicationsPranav Ashar, Sharad Malik. dac 1994: 77-80 [doi]

1993

Path-delay-fault testability properties of multiplexor-based networksPranav Ashar, Srinivas Devadas, Kurt Keutzer. integration, 15(1):1-23, 1993. [doi]

Gate-Delay-Fault Testability Properties of Multiplexor-Based NetworksPranav Ashar, Srinivas Devadas, Kurt Keutzer. fmsd, 2(1):93-112, 1993.

Technology Mapping for Lower PowerVivek Tiwari, Pranav Ashar, Sharad Malik. dac 1993: 74-79 [doi]

1992

Boolean satisfiability and equivalence checking using general Binary Decision DiagramsPranav Ashar, Abhijit Ghosh, Srinivas Devadas. integration, 13(1):1-16, 1992. [doi]

Exploiting multi-cycle false paths in the performance optimization of sequential circuitsPranav Ashar, Sujit Dey, Sharad Malik. iccad 1992: 510-517 [doi]

1991

1990

A Unified Approach to the Decomposition and Re-Decomposition of Sequential MachinesPranav Ashar, Srinivas Devadas, A. Richard Newton. dac 1990: 601-606 [doi]

Testability driven synthesis of interacting finite state machinesPranav Ashar, Srinivas Devadas, A. Richard Newton. iccd 1990: 273-276 [doi]

Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and TestPranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton. iccad 1990: 84-87

1989

Optimum and heuristic algorithms for finite state machine decomposition and partitioningPranav Ashar, Srinivas Devadas, A. Richard Newton. iccad 1989: 216-219 [doi]

1988

Magnitude locked loopK. Radhakrishna Rao, Pranav Ashar. pieee, 76(2):201-203, 1988. [doi]

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