Table of Contents

• A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia ApplicationsTakashi Miyamori, Kunle Olukotun. 2-11 [doi]
• Exploring Optimal Cost-Performance Designs for Raw MicroprocessorsCsaba Andras Moritz, Donald Yeung, Anant Agarwal. 12-27 [doi]
• The NAPA Adaptive Processing ArchitectureCharlé R. Rupp, Mark Landguth, Tim Garverick, Edson Gomersall, Harry Holt, Jeffrey M. Arnold, Maya Gokhale. 28 [doi]
• A Stream-Based Configurable Computing Radio TestbedSteven Swanchara, Scott J. Harper, Peter M. Athanas. 40-47 [doi]
• Architecture and Design of GE1, a FCCM for Golomb Ruler DerivationApostolos Dollas, Euripides Sotiriades, Apostolos Emmanouelides. 48 [doi]
• New FPGA Architecture for Bit-Serial Pipeline DatapathAkihisa Ohta, Tsuyoshi Isshiki, Hiroaki Kunieda. 58-67 [doi]
• Plastic Cell Architecture: Towards Reconfigurable Computing for General-PurposeKouichi Nagami, Kiyoshi Oguri, Tsunemichi Shiozawa, Hideyuki Ito, Ryusuke Konishi. 68-77 [doi]
• The Design and Implementation of a Context Switching FPGAStephen M. Scalera, Jóse R. Vázquez. 78 [doi]
• A Run-Time Reconfigurable Engine for Image InterpolationRhett D. Hudson, David I. Lehn, Peter M. Athanas. 88-95 [doi]
• Hardware/Software Integration in Solar PolarimetryMark Shand, Laurent Moll. 96 [doi]
• An Overview of the COBRA-ABS High Level Synthesis System for Multi-FPGA SystemsAndrew A. Duncan, David C. Hendry, Peter Gray. 106-115 [doi]
• Specifying and Compiling Applications for RaPiDDarren C. Cronquist, Paul Franklin, Stefan G. Berg, Carl Ebeling. 116-125 [doi]
• NAPA C: Compiling for a Hybrid RISC/FPGA ArchitectureMaya Gokhale, Janice M. Stone. 126 [doi]
• Configuration Compression for the Xilinx XC6200 FPGAScott Hauck, Zhiyuan Li, Eric J. Schwabe. 138-146 [doi]
• Automating Production of Run-Time Reconfigurable DesignsNabeel Shirazi, Wayne Luk, Peter Y. K. Cheung. 147 [doi]
• Object Oriented Circuit-Generators in JavaMichael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek. 158-166 [doi]
• PAM-Blox: High Performance FPGA Design for Adaptive ComputingOskar Mencer, Martin Morf, Michael J. Flynn. 167-174 [doi]
• JHDL - An HDL for Reconfigurable SystemsPeter Bellows, Brad L. Hutchings. 175 [doi]
• Accelerating Boolean Satisfiability with Configurable HardwarePeixin Zhong, Margaret Martonosi, Pranav Ashar, Sharad Malik. 186-195 [doi]
• Dynamic Circuit Generation for Solving Specific Problem Instances of Boolean SatisfiabilityAzra Rashid, Jason Leonard, William H. Mangione-Smith. 196 [doi]
• A Re-evaluation of the Practicality of Floating-Point Operations on FPGAsWalter B. Ligon III, Scott McMillan, Greg Monn, Kevin Schoonover, Fred Stivers, Keith D. Underwood. 206-215 [doi]
• A Variable Long-Precision Arithmetic Unit Design for Reconfigurable Coprocessor ArchitecturesAlexandre F. Tenca, Milos D. Ercegovac. 216-225 [doi]
• A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA StructureSimon D. Haynes, Peter Y. K. Cheung. 226 [doi]
• Accelerating Adobe Photoshop with the Reconfigurable LogicSatnam Singh, Robert Slous. 236-244 [doi]
• Analysis of the XC6000 Architecture for Embedded System DesignKarlheinz Weiß, Ronny Kistner, Arno Kunzmann, Wolfgang Rosenstiel. 245 [doi]
• A FPGA Based Forth MicroprocessorPhilip Heng Wai Leong, P. K. Tsang, T. K. Lee. 254-255 [doi]
• PROGRAPE-1: A Programmable Special-Purpose Computer for Many-Body SimulationsTsuyoshi Hamada, Toshiyuki Fukushige, Atsushi Kawai, Joshiyuki Makino. 256-257 [doi]
• RVC - A Reconfigurable Coprocessor for Vector Processing ApplicationsJosé Carlos Alves, José Silva Matos. 258-259 [doi]
• The Systolic Array Genetic Algorithm, An Example of Systolic Arrays as a Reconfigurable Design MethodologyI. M. Bland, Graham M. Megson. 260-261 [doi]
• 50 kHz Pattern Recognition on the Large FPGA Processor Enable++Andreas Kugel, Klaus Kornmesser, R. Lay, J. Ludvig, Reinhard Männer, K. H. Noffz, Stephan Rühl, M. Sessler, Harald Simmler, Holger Singpiel. 262 [doi]
• An Embedded DRAM-FPGA Chip with Instantaneous Logic ReconfigurationMasato Motomura, Yoshiharu Aimoto, Atsufkni Shibayama, Yoshikazu Yabe, Masakazu Yamashina. 264-266 [doi]
• Mapping the MD5 Hash Algorithm onto the NAPA ArchitectureJeffrey M. Arnold. 267-268 [doi]
• General Purpose vs. Custom FCCM s: a Comparison of Splash2, Quickturn RPM, and GE1 for Golomb Ruler DerivationApostolos Dollas, Euripides Sotiriades, Apostolos Emmanouelides, Lee House. 269-270 [doi]
• An Architecture Simulator for National Semiconductor s Adaptive Processing Architecture (NAPA)Jeffrey M. Arnold. 271-272 [doi]
• Benchmarking Technology for Configurable Computing SystemS. Kumar, Luiz Pires, D. Pandalai, M. Vojta, J. Golusky, S. Wadi, Henk A. E. Spaanenburg. 273-274 [doi]
• Reconfigurable Processor Architectures Exploiting High Bandwidth Optical ChannelsM. F. Sakr, Steven P. Levitan, C. Lee Giles, Donald M. Chiarulli. 275 [doi]
• Some Applications of FPGAs in Bio-Inspired HardwareAndré Stauffer, Moshe Sipper, Andrés Pérez-Uribe. 278-279 [doi]
• A Prototype System for Rapid Application Development using Dynamically Reconfigurable HardwareJoão Canas Ferreira, José Silva Matos. 280-281 [doi]
• Scalable Network Based FPGA Accelerators for an Automatic Target Recognition ApplicationRuth Sivilotti, Young Cho, Wen-King Su, Danny Cohen, Brian Bray. 282-283 [doi]
• An FPGA Implementation of GENET for Solving Graph Coloring Problems T. K. Lee, Philip Heng Wai Leong, K. H. Lee, K. T. Chan, S. K. Hui, H. K. Yeung, M. F. Lo, J. H. M. Lee. 284-285 [doi]
• SLAAC: A Distributed Architecture for Adaptive ComputingStephen P. Crago, Brian Schott, Robert Parker. 286-287 [doi]
• RENCO: A Reconfigurable Network ComputerJacques-Olivier Haenni, Jean-Luc Beuchat, Eduardo Sanchez. 288-289 [doi]
• Hardware Implementation of Generalized Profile Search on the GENSTORM MachineEmeka Mosanya, Jean-Michel Puiatti, Eduardo Sanchez. 290-291 [doi]
• FPGA-Based Architecture Evaluation of Cryptographic Coprocessors for SmartcardsHagen Ploog, Dirk Timmermann. 292-293 [doi]
• Characterization and Parameterization of a Pipeline Reconfigurable FPGAMatthew Moe, Herman Schmit, Seth Copen Goldstein. 294 [doi]
• A FPGA-Based Custom Computing System for Solving the Assignment ProblemDonald L. Hung, Jun Wang. 298-299 [doi]
• Circlets: Circuits as AppletsGordon J. Brebner. 300-301 [doi]
• Dynamic Reconfiguration to Support Concurrent ApplicationsJack S. N. Jean, Karen A. Tomko, Vikram Yavagal, Robert Cook, Jignesh Shah. 302-303 [doi]
• A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable ComputingPascal Poiré, Marc-André Cantin, Hervé Daniel, Yves Blaquière, Yvon Savaria. 304-305 [doi]
• Frequency-Domain Sonar Processing in FPGAs and DSPsPaul Graham, Brent E. Nelson. 306-307 [doi]
• Dynamic Specialization of XC6200 FPGAs by Partial EvaluationNicholas McKay, Thomas F. Melham, Kong Woei Susanto, Satnam Singh. 308-309 [doi]
• DES Key Breaking, Encryption and Decryption on the XC6216Tom Kean, Ann Duncan. 310-311 [doi]
• An Effective Design System for Dynamically Reconfigurable ArchitecturesSriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri. 312-313 [doi]
• Mapping Homogeneous Computations onto Dynamically Configurable Coarse-Grained ArchitecturesAndreas Dandalis, Viktor K. Prasanna. 314 [doi]
• Fast Partial Reconfiguration for FCCMsSakir Sezer, Roger Woods, Jean-Paul Heron, Alan Marshall. 318-319 [doi]
• Reconfigurable Hardware as Shared Resource for Parallel ThreadsGunter Haug, Wolfgang Rosenstiel. 320-321 [doi]
• Digit-Serial DSP Library for Optimized FPGA ConfigurationHanho Lee, Gerald E. Sobelman. 322-323 [doi]
• A Methodology for Task Based Partitioning and Scheduling of Dynamically Reconfigurable SystemsPedro Merino, Margarida F. Jacome, Juan Carlos López. 324-325 [doi]
• High Level Synthesis for Designing Custom Computing HardwareGoran Doncev, Miriam Leeser, Shantanu Tarafdar. 326-328 [doi]
• Temporal Partitioning and Scheduling for Reconfigurable ComputingKarthikeya M. Gajjala Purna, Dinesh Bhatia. 329-330 [doi]
• Implementation of RNS Addition and RNS Multiplication into FPGAsLuiz Maltar, Felipe M. G. França, Vladimir Castro Alves, Cláudio L. Amorim. 331-332 [doi]
• A Scalable FIR Filter Using 32-bit Floating-Point Complex Arithmetic on a Configurable Computing MachineAl Walters, Peter Athanas. 333-334 [doi]
• Reconfigurable Computing for Space-Time Adaptive ProcessingNikhil D. Gupta, John K. Antonio, Jack M. West. 335-336 [doi]
• Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic BlocksManoucher Shaditalab, Guy Bois, Mohamad Sawan. 337-338 [doi]
• Implementing C Algorithms in Reconfigurable Hardware Using C2VerilogDonald Soderman, Yuri Panchul. 339 [doi]