José Silva Matos - researchr alias

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Viewing Publication 1 - 23 from 23

2016

Scalable hardware architecture for disparity map computation and object location in real-timePedro Miguel Santos, João Canas Ferreira, José Silva Matos. jrtip, 11(3):473-485, 2016. [doi]

2015

MICPRO DSD 2014 special issueFrancesco Leporati, José Silva Matos. mam, 39(8):961, 2015. [doi]

2014

MICPRO DSD 2013 Special IssueJosé Silva Matos, Francesco Leporati. mam, 38(8):741-742, 2014. [doi]

2005

A processor for testing mixed-signal cores in System-on-ChipFrancisco Duarte, José Machado da Silva, José Carlos Alves, G. A. Pinho, José Silva Matos. dsdm 2005: 184-191 [doi]

2004

A Development Support System for Applications That Use Dynamically Reconfigurable HardwareJoão Canas Ferreira, José Silva Matos. fpl 2004: 886-890 [doi]

2001

ADC testing using joint time-frequency analysisHélio Mendonça, José Machado da Silva, José Silva Matos. csi, 23(2):129-135, 2001. [doi]

2000

Mixed-Signal BIST Using Correlation and Reconfigurable HardwareJosé Machado da Silva, J. Soeiro Duarte, José Silva Matos. date 2000: 744 [doi]

1999

FAFNER-Accelerating Nesting Problems with FPGAsJosé Carlos Alves, João Canas Ferreira, C. Albuquerque, José F. Oliveira, J. Soeiro Ferreira, José Silva Matos. fccm 1999: 168 [doi]

1998

RVC - A Reconfigurable Coprocessor for Vector Processing ApplicationsJosé Carlos Alves, José Silva Matos. fccm 1998: 258-259 [doi]

A Prototype System for Rapid Application Development using Dynamically Reconfigurable HardwareJoão Canas Ferreira, José Silva Matos. fccm 1998: 280-281 [doi]

Mixed hardware/software applications on dynamically reconfigurable hardwareJoão Canas Ferreira, José Silva Matos. icecsys 1998: 97-100 [doi]

Flexible hardware acceleration for nesting problemsJoão Canas Ferreira, José Carlos Alves, C. Albuquerque, José Fernando Oliveira, José Soeiro Ferreira, José Silva Matos. icecsys 1998: 345-348 [doi]

Computer Organisation, Programming and Benchmarking - IntroductionJosé Silva Matos. vecpar 1999: 331-333

Mixed-Signal Board Level DfT Techniques Using IEEE P1149.4José Silva Matos, José Machado da Silva. icecsys 1998: 441-446 [doi]

1997

A vector architecture for higher-order moments estimationJosé Carlos Alves, André T. Puga, Luís Corte-Real, José Silva Matos. icassp 1997: 4145-4148 [doi]

Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 InfrastructureJosé Machado da Silva, Ana C. Leão, José Silva Matos, José Carlos Alves. itc 1997: 509-517

1996

ProHos-1 - A Vector Processor for the Efficient Estimation of Higher-Order MomentsJosé Carlos Alves, André T. Puga, Luís Corte-Real, José Silva Matos. vecpar 1997: 96-107

Mixed current/voltage observation towards effective testing of analog and mixed-signal circuitsJosé Machado da Silva, José Silva Matos, Ian M. Bell, Gaynor E. Taylor. et, 9(1-2):75-88, 1996. [doi]

Evaluation of iDD/vOUT Cross-Correlation for Mixed Current/Voltage Testing of Analogue and Mixed-Signal CircuitsJosé Machado da Silva, José Silva Matos. date 1996: 264-269 [doi]

1994

Architecture of test support ICs for mixed-signal testingJosé Silva Matos, João Canas Ferreira, Ana C. Leão, J. Machado Silva. vts 1994: 240-246 [doi]

An Approach to Testability Improvement of Mixed-Signal BoardsJosé Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva. iscas 1994: 161-164

1993

Control and Observation of Analog Nodes in Mixed-Signal BoardsJosé Silva Matos, Ana C. Leão, João Canas Ferreira. itc 1993: 323-331

1992

A Boundary Scan Test Controller for Hierarchical BISTJosé M. M. Ferreira, Filipe S. Pinto, José Silva Matos. itc 1992: 217-223

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