Abstract is missing.
- Double Broadband Matching of a Lowpass Generator and a Lowpass Load by Equal Minima Gain FunctionsCatherine Dehollain, Jacques Neirynck. 1-4
- Determination of Circular Arc Length and Midpoint by Hough TransformSoo-Chang Pei, Ji-Hwei Horng. 1-4
- Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPSEby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan. 1-6
- EDLICS: A New Relaxation-Based Electrical Circuit Simulation TechniqueJai-Cheol Lee, Yu Hen Hu. 1-4
- Invariant Sets for General Second-Order Lowpaws Delta-Sigma Modulators with DC InputsBo Zhang, Montgomery Goodson, Richard Schreier. 1-4
- The Mahalanobis Distance Hough Transform with Extended Kalman Filter RefinementChengping Xu, Sergio A. Velastin. 5-8
- Design of II Impedance Matching NetworksYichuang Sun, J. K. Fidler. 5-8
- Characterization of ADCs Using a Non-Iterative ProcedureDonald M. Hummels, F. H. Irons, R. Cook, Ioannis Papantonopoulos. 5-8
- Sinusoidal Excitation on the Chua s Circuit Simulation of Limit Cycles and ChaosErik Lindberg. 5-8
- Object Recognition with a 2-D Hough DomainPui-Kin Ser, Wan-Chi Siu. 9-12
- Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective TraceMasakatsu Nishigaki, Nobuyuki Tanaka, Hideki Asai. 9-12
- A Two Stage Structure for High Order Multi-Bit Sigma-Delta ADC with Multiplier-less Digital Correction LogicBaher Haroun, Chao Hua Wu. 9-12
- General Formulas for the Ideal Flat Gain in the Case of Double Broadband MatchingCatherine Dehollain, Jacques Neirynck. 9-12
- A Glitch-Free Single-Phase CMOS DFF for Gigahertz ApplicationsQiuting Huang, Robert Rogenmoser. 11-14
- An Analytical Least Squares Hough TransformMarcello Fini, Sergio A. Velastin. 13-16
- Circuit Model of Coupled Transmission Lines with Frequency-Dependent TransformationsQingjian Yu, Omar Wing. 13-16
- Dynamic Characteristics of a Digital TransducerPatrick A. Littlehales, Christopher P. Lewis, Steven R. Bishop. 13-16
- New CMOS Differential Logic Circuits for True-Single-Phase Pipelined SystemsHong-Yi Huang, Chung-Yu Wu. 15-18
- A New Nonlinear Algorithm for the Removal of Impulse Noise from Highly Corrupted ImagesSanjit K. Mitra, Tian-Hu Yu. 17-20
- Linear Phase Cosine Modulated Maximally Decimated Filter Banks with Perfect ReconstructionYuan-Pei Lin, P. P. Vaidyanathan. 17-20
- Chaotic Signals Generated by Digital Filter OverflowKristina Kutzer, Wolfgang M. Schwarz, Anthony C. Davies. 17-20
- Strange Behavior in Inifinite and Transfinite NetworksArmen H. Zemanian. 21-24
- Dynamics of a Simple Hysteresis NetworkKenya Jin no, Toshimichi Saito. 21-24
- Analysis of the Transient Bahviour of Unconstrained Frequency-Domain Adaptive FiltersPius Estermann, August Kaelin. 21-24
- Detection and Interpolation of Replacement Noise in Motion Picture Sequences Using 3D Autoregressive NodellingAnil C. Kokaram, Peter J. W. Rayner. 21-24
- Feedback-Controlled Enhance-Pull-Down BiCMOS for Sub-3-V Digital CircuitYuh-Kuang Tseng, Kuo-Hsing Cheng, Chung-Yu Wu. 23-26
- Efficient Gabor Filter Design Using Rician Output StatisticsThomas P. Weldon, William E. Higgins, Dennis F. Dunn. 25-28
- Decomposed Parametric Form of the State Model of a Piecewise-Linear SystemJaromír Brzobohaty, Jirí Pospísil, Zdenek Kolka. 25-28
- Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression GenerationFrancisco V. Fernández, Piet Wambacq, Georges G. E. Gielen, Ángel Rodríguez-Vázquez, Willy M. C. Sansen. 25-28
- Predicting Complex Chaotic Time Series via Complex Valued MLPsPaolo Arena, Luigi Fortuna, Maria Gabriella Xibilia. 29-32
- Waveform Relaxation Synthesis of Distributed-Lumped Network Characteristic ModelsFung-Yuel Chang. 29-32
- PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer DesignBeomsup Kim, Todd C. Weigandt, Paul R. Gray. 31-34
- A Discrete-Time Equivalent System Approach to the Periodic Response of Nonlinear Autonomous CircuitsPere Palà-Schönwälder, J. M. Miró Sans. 33-36
- An Approach to Integrated Numerical & Symbolic Circuit AnalysisWlodzimierz M. Zuberek, A. Konczykowska, D. Martin. 33-36
- Analytic, Rational Approximation of square root of sOmar Wing. 33-35
- Correlation-feedback Approach to Computation of Optical FlowJ. N. Pan, Yun Q. Shi, Chang-Qing Shu. 33-36
- On Perfect-Reconstruction Allpass-Based Cosine-Modulated IIR Filter BanksTruong Q. Nguyen, Timo I. Laakso, T. Engin Tuncer. 33-36
- A New Retiming Algorithm for Circuit DesignSven Simon, Ernst G. Bernard, Matthias Sauer, Josef A. Nossek. 35-38
- The Multiple Input Floating Gate MOS Differential Amplifier An Analog Computational Building BlockKewei Yang, Andreas G. Andreou. 37-40
- On the Design of a Jitter-Tolerant Synchronisation Subsystem for Optical Fibre PPMJaafar M. H. Elmirghani, Robert A. Cryan. 37-40
- Order of N Complexity Transform Domain Adaptive FiltersBehrouz Farhang-Boroujeny. 37-40
- Design of an ASIC to Implement a New Data Tranfer Protocol for High Energy PhysicsV. K. Raj, R. V. Idate, A. W. Booth, M. Botlo, J. Dorenbosch, E. C. Milner, E. M. Wang. 39-42
- Adaptive Volterra-DFE and Timing Recovery in Digital Magnetic Recording SystemJui-Yuan Lin, Che-Ho Wei. 41-44
- Convergence Analysis of Gradient Adaptive Algorithms for Arbitrary InputsJinhui Chao, Shinobu Kawabe, Shigeo Tsujii. 41-44
- Generalized Diakoptic Analysis for Large-Scale Piecewise-Linear Nonlinear Electircal CircuitsMihai Iordache, Razvan Iordache. 41-44
- Adaptive Smart Imager for Pulse Structured Light VisionF. Lavainne, Yang Ni, Francis Devos, P. de Came. 41-44
- 5.8Gb/s 16: 1 Multiplexer and 1: 16 Demultiplexer Using 1.2µm BiCMOSJacob Midtgaard, Christer Svensson. 43-46
- Adaptive Video Coding using Mixed-Domain Filter Banks having Optimal-Shaped SubbandsBo Liu, Leonard T. Bruton. 45-48
- Symbol Timing Recovery in Digital Subscriber Loops in the Presence of Residual Echo & Impulsive NoiseErdal Panayirci. 45-52
- Storage Enhancement Techniques for Digital Memory Based, Analog Computational EnginesHitoshi Miwa, Kewei Yang, Philippe O. Pouliquen, Nagendra Kumar, Andreas G. Andreou. 45-48
- Algorithms for the Automatic Design of the Decomposed state Model of an One-Dimensional Piecewise-Linear SystemZdenek Kolka, Jirí Pospísil. 45-48
- A Time-Delay Differential-Algebraic Phasor Formulation of the Large Power System DynamicsVaithianathan Venkatasubramanian, Heinz Schättler, John Zaborszky. 49-52
- On the Feasibility of SI for low-Power VLSI Biomedical Signal ProcessingGerson A. S. Machado, Chris Toumazou, Tor Sverre Lande. 49-52
- A Power-Saving Technique for Bit-Serial DSP ASICsNianxiong Tan, Sven Eriksson, Lars Wanhammar. 51-54
- An Evolutionary Search Algorithm for Adaptive IIR EqualizerSin Chun Ng, C. Y. Chung, Shu Hung Leung, Andrew Luk. 53-56
- A Comparison of Algorithms for Least Absolute Value State Estimation in Electoric Power NetworksA. Bagchi, K. A. Clements, P. W. Davis, F. H. Maurais. 53-56
- Design of Novel Serial-Parallel Inner-Product ProcessorsMaher N. Fahmi, Fayez El Guibaly, Sreenivasachar Sunder, Dale J. Shpak. 55-58
- On the Estimation of Bulk Delay & Length of Dispersive Region in Echo CancellationSimon S. F. Hau, Yuk-Hee Chan, Peter C. K. Liu. 57-60
- A Homotopy Continuation Mapping for the Steiglitz-McBride Adaptive AlgorithmSergio L. Netto, Panajotis Agathoklis. 57-60
- A Unified Algorithm for Estimation and Scheduling in Data Path SynthesisYuan Hu, Bradley S. Carlson. 57-60
- A Method for Evaluating a Mapping Parameter for Power System Dynamic Stability AnalysisHiroyuki Mori, Junya Kanno. 57-60
- Area-Time Analysis of Carry Lookahead Adders Using Enhanced Multiple Output Domino LogicJune Wang, Zhongde Wang, Graham A. Jullien, William C. Miller. 59-62
- ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS CircuitsSantanu Dutta, Sudip Nag, Kaushik Roy. 61-64
- Closed-Loop Input Impedance of PWM Buck-Derived DC-DC ConvertersMarian K. Kazimierczuk, Robert Cravens II, Alberto Reatti. 61-64
- Fault Detection in Linear Bipolar ICs: Comparative Results Between Power Supply Current and Output Voltage MeasurementsD. K. Papakostas, A. A. Hatzopoulos. 61-64
- Parameter Tracking of the Poly-Phase Structure Adaptive Filtering AlgorithmUmashankar Iyer, Majid Nayeri, Hiroshi Ochi. 61-64
- Fault-Tolerant Architectures for Shared Buffer Memory SwitchYeong-Fong Lin, C. Bernard Shung. 61-64
- Pseudo-Random Vector Compaction for Sequential TestabilityNaim Ben Hamida, Bozena Kaminska, Yvon Savaria. 63-66
- High Level Synthesis with Testability ConstraintsNaim Ben Hamida, Bozena Kaminska. 65-68
- A VLSI Systolic Array Architecture for Lempel-Ziv-Based Data CompressionBongjin Jung, Wayne Burleson. 65-68
- An Algorithm for Solving the Equations of Monotone Nonlinear Resistive NetworksIrwin W. Sandberg. 65-68
- 2-D Adaptive State-Space Digital Filters using LMS AlgorithmMitsuji Muneyasu, Takao Hinamoto. 65-68
- Measuring the Impulse Response of Linear Systems using an Analog CorrelatorHarry W. Li, Michael J. Dallabetta, Howard B. Demuth. 65-68
- A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural ApproachSarwono Sutikno, Mineo Kaneko, Mahoki Onoda. 67-70
- A Neural Network for Blind Signal SeparationXie-Ting Ling, Yih-Fang Huang, Ruey-Wen Liu. 69-72
- Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type FaultsShujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller. 69-72
- Adaptive Impedance MatchingAnees S. Munshi, David A. Johns, Adel S. Sedra. 69-72
- Performance Measurements in a Manufacturing Communication SystemCélio V. N. de Albuquerque, Marcelo D. Nunes, Otto Carlos Muniz Bandeira Duarte. 69-72
- A Method of Representative Fault Selection in Digital Circuits for ATPGAkachai Sang-In, Peter Y. K. Cheung. 73-76
- Quantization Noise of 1-Bit Double-Loop Sigma-Delta ModulatorA. Namdar, B. H. Leung. 73-76
- Modular Realization of Bandstop and Bandpass FIR Digital FiltersSaed Samadi, Akinori Nishihara, Nobuo Fujii. 73-76
- ASIC Design of a Generalized Covariance Matrix Processor for DOA AlgorithmsM. M. Jamali, S. Ravindranath, Subhash C. Kwatra, A. G. Eldin. 75-78
- Studies on the Stability of Two Dimsensional Analog Nonlinear CircuitsHari C. Reddy, George S. Moschytz. 77-80
- A New Strategy for Test Pattern Generation in Sequential CircuitsBeom-Ik Cheon, Walter Anheier, Rainer Laur. 77-80
- Design and Implementation of Cosine-Modulated Dimensional Perfect Reconstruction FIR Filter BanksMasaaki Ikehara. 77-80
- A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower LimitYukiya Miura, Sachio Naito, Kozo Kinoshita. 77-80
- Systematic Design of Multi-Modulus/Multi-Function Residue Number System ProcessorsVassilis Paliouras, Thanos Stouraitis. 79-82
- Two-Dimensional Sequential Array Architectures: Design for Testability ApproachesCristiana Bolchini, Franco Fummi, Donatella Sciuto. 81-84
- Rigorous and Realistic Control of Piecewise Linear ChaosToshimichi Saito, Kunihiko Mitsubori. 81-84
- An Improved Biasing Circuit for High Input CMR Op AmpsJ. Francisco Duque-Carrillo, R. Pérez-Aloe, J. M. Valverde. 81-84
- Increasing the Speed and Saving Mulitpliers in Block Parallel Digital Filters by a Linear TransformationMarkus Wintermantel, Ernst Lüder. 81-84
- CMOS Reliability Improvements Through a New Fault Tolerant TechniqueCristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli. 83-86
- Bit-Serial Generalized Median FiltersBarun K. Kar, Khadem M. Yusuf, Dhiraj K. Pradhan. 85-88
- A Simple and Robust Method for Controlling Chaotic SystemsHervé Dedieu, Maciej Ogorzalek. 85-88
- Large Bandwidth BiCMOS Operational Amplifiers for SC-Video-ApplicationsG. Nebel, U. Kleine, Hans-Jörg Pfleiderer. 85-88
- A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial CircuitsJer Min Jou, Shung-Chih Chen, Ren-Der Chen. 85-88
- High Throughput CORDIC-Based Systolic Array Design for the Discrete Cosine TransformJue-Hsuan Hsiao, Liang-Gee Chen, Tzi-Dar Chiueh, Chun-Te Chen. 85-88
- Reconfigurable Linear Feedback Register Design, Analysis & ApplicationsRandy E. Bolling, Sami A. Al-Arian. 87-90
- A 50 MHz CMOS Differential Amplifier Channel for a Laser Range Finding DeviceTarmo Ruotaslainen, Juha Kostamovaara. 89-92
- Controlling Chaotic Motions in Chua s Circuit via TunnelsMakoto Itoh, Hiroyuki Murakami, Leon O. Chua. 89-92
- A Redefinable Symbolic Simulation Technique to Testability Design Rules CheckingM. Hirech, O. Florent, Alain Greiner, E. Rejouan. 89-92
- Pipelined Recursive Digital Filters: Clustered Look-Ahead and Scattered Look-Ahead TechniquesKyungHi Chang, Jinwoong Kim. 89-92
- Novel Sorting Netowrk-Based Architectures for Rank Order FiltersChaitali Chakrabarti, Li-Yu Wang. 89-93
- Analog Implementation of Class-IV Partial-Response Viterbi DetectorM. H. Shakiba, David A. Johns, Kenneth W. Martin. 91-94
- Associative Memory Architecture for Video CompressionFayez M. Idris, Sethuraman Panchanathan. 93-96
- A Novel Input Differential Pair for Improved Linearity Buffer and S/H Amplifier DesignKhayrollah Hadidi, Gabor C. Temes. 93-96
- Modelling Sound with ChaosJonathan Mackenzie, Mark B. Sandler. 93-96
- Gate Level Optimisation of Primitive Operator Digital Filters using a Carry Save DecompositionDavid R. Bull, Graham Wacey. 93-96
- Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation ModelMineo Kaneko, Kazuhiro Sakaguchi. 93-96
- Real Time Solution of Laplace equation using Analog VLSI CircuitsJaime Ramírez-Angulo, Kevin Treece, Mark DeYong. 95-98
- Optimal Placement of Heat Dissipating ElementsMariusz Ziólko. 97-99
- VHF Fully-Differential Linearized CMOS Transconductance Element and its ApplicationsStanislaw Szczepanski. 97-100
- IC Implementation of Switched-Capacitor Chaotic NeuronYoshihiko Horio, Ken Suyama. 97-100
- A New Design for A Frame Sampling SynchronizerJacqueline Walker, Antonio Cantoni. 97-100
- A Comparison of Analog DFE Architectures for Disk-Drive ApplicationsJames E. C. Brown, Paul J. Hurst, Lawrence Der, Iskender Agi. 99-102
- A Digital Fuzzy-Logic Controller with a Simple ArchitectureFrancisco Colodro Ruiz, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo. 101-104
- Nonlinear Dynamics of Chaotic Double-Loop Sigma Delta ModulationOrla Feely. 101-104
- Current Feedback Amplifiers Based Sinusoidal OscillatorsS. Celma, Alfonso Carlosena, P. A. Martínez. 101-104
- Integration System as Adaptive Control SystemH. Mauritz, Wolfgang Mathis. 101-104
- Design of High Accuracy Video ComparatorGiuseppe Caiulo, Franco Maloberti, Guido Torelli. 101-104
- Pulse-Stream Circuits for On-Chip Learning in Analogue VLSI Neural NetworksRobin Woodburn, H. Martin Reekie, Alan F. Murray. 103-106
- A Class D Type High Frequency Tuned Power Amplifier with Class E Switching ConditionsHirotaka Koizumi, Minoru Iwadare, Shinsaku Mori, Kazunaga Ikeda. 105-108
- Region Definition of Minimizing the Number of Switchboxes and Ordering AssignmentJin-Tai Yan, Pei-Yung Hsiao. 105-108
- Performance of Yamakawa s Chaotic Chips and Chua s Circuits for Secure CommunicationsMakoto Itoh, Hiroyuki Murakami, Leon O. Chua. 105-108
- Hybrid Additive Random Sampling and its RealizationK. C. Lo, Alan Purvis. 105-108
- High Speed Monolithic Read-Out System for High Energy Physics ExperimentsA. Baschirotto, M. Bosetti, R. Castello, A. Gola, G. Pessina, P. Rancoita, M. Rattaggi, M. Redaelli, G. Terzi. 107-110
- Analysis and Design of Low-Q and High-Q Filters Derived from Complementary Pole-Pair FiltersK. R. Pai, K. V. V. Murthy, V. Ramachandran. 109-112
- Designing DSP-based systems using Multiple Processor Hardware PlatformsMoe Razaz, Keith Marlow. 109-112
- Inverse Problem and Approximation of Fractal-like ImagesRoberto Rinaldo, Avideh Zakhor. 109-112
- Multimode Chaos in Two Coupled Chaotic Oscillators with Hard NonlinearitiesYoshifumi Nishio, Akio Ushida. 109-112
- Approximate Computation of Signal Characteristics of On-chip RC Interconnect TreesN. S. Nagaraj, Paul Krivacek, Mark Harward. 109-112
- Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer DesignBrian S. Cherkauer, Eby G. Friedman. 111-114
- An Improved Wavelet-Fractal CoderRoberto Rinaldo, Giancarlo Calvagno. 113-116
- Torus Doubling and Hyperchaos in a Five Dimensional Hysteresis CircuitKunihiko Mitsubori, Toshimichi Saito. 113-116
- An Accurate and Matching-Free Threshold Voltage Extraction Scheme for MOS TransistorsChong-Gun Yu, Randall L. Geiger. 115-118
- New Algorithms in Piecewise Linear Resistive SimulationJ. Soares Augusto, C. F. Beltrá Almeida. 117-120
- Design of a Mesh-Type Systolic Array Architecture for the Fast Computation of the Single Linkage AlgorithmM. Y. Niamat, M. M. Jamali, P. Y. Mohanty. 117-120
- Inversion of unimodular Matrices via State-Space ApproachHung-Chou Chen, Fan-Ren Chang, Gwo-Jeng Ju. 117-120
- Automated Placement for a Leaf Cell GeneratorDilvan de Abreu Moreira, Les T. Walczowski. 117-120
- Continuous-Time Adaptive Delay SystemShih-Chii Liu, Carver Mead. 119-122
- Statistical Characterization and Modeling of Analog Functional BlocksMing Qu, M. A. Styblinski. 121-124
- A Method for Solving Complex Linear Equation of AC Network by Interval ComputationKohshi Okumura, Satoru Higashino. 121-124
- Floating Point Addition Errors and their Effect on the Roundoff Noise in Digital Signal ProcessingFrank Hartwig, Arild Lacroix. 121-124
- An Analysis of Finite Register Length Effects on Arithmetic CodesShaw-Min Lei. 121-124
- Analysis of Bifurcation Points of Nonlinear Resistive Circuits by Curve Tracing MethodAkio Ushida. 121-124
- A Low-Cost Strategy for Testing Analog FiltersDiego Vázquez, Adoración Rueda, José L. Huertas. 123-126
- Stochastic Interpolation Model Scheme for Statistical Circuit DesignJin-Qin Lu, Kimihiro Ogawa, Takehiko Adachi, Andrzej J. Strojwas. 125-128
- Conditions for Hurwitz Stability of Interval MatricesEzra Zeheb. 125-127
- A Programmable Image Processing System using FPGAShing-Chow Chan, H. O. Ngai, Ka-Leung Ho. 125-128
- Near-Lossless Compression of Continuous-Tone Still Images Using Fuzzy Logic Notions and the Binary Arithmetic Coder (Q-Coder)John Ant. Hallas, Michael K. Birbas, Alexios N. Birbas, John C. Kikidis, Constantinos E. Goutis. 125-128
- Hybrid Algorithm for the Computation of the Matrix Polynomial using a Fractal Number SystemVassil S. Dimitrov, Todor Cooklev. 129-132
- The Huber Concept in Device Modeling, Circuit Diagnosis and Design CenteringJ. W. Bandler, S. H. Chen, R. M. Biernacki, Kim Halskov Madsen. 129-132
- Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to ArchitecturesFrancky Catthoor, Ed F. Deprettere, Yu Hen Hu, Jan M. Rabaey, Heinrich Meyr, Lothar Thiele. 129-136
- A Variable Dimension Newton MethodS. W. Ng. 129-132
- The Determination of the Searching Sequence for VQ EncodingYuk-Hee Chan, Wan-Chi Siu. 129-132
- High Sample Rate Architectures for Block Adaptive FiltersSrikanth Karkada, Chaitali Chakrabarti, Andreas Spanias. 131-134
- Image Coding Using Vector Filter Bank and Vector QuantizationJohn Wus, Weiping Li, Ya-Qin Zhang. 133-136
- Statistical Constrained Optimization of Analog CMOS Circuits using Empirical Performance ModelsHua Su, Christopher Michael, Mohammed Ismail. 133-136
- Lossy Transmission Line Response via Numerical Laplace Transform InversionIvan A. Maio, Flavio G. Canavero. 133-136
- A Current-Mode DTCNN Universal Chip Hubert Harrer, Josef A. Nossek, Tamás Roska, Leon O. Chua. 135-138
- On the Double Biliniear Transformation and Nonessential Singularities of the Second Kind at InfinityS. A. Yost, Peter H. Bauer, Kasyapa Balemarthy. 137-140
- On Optimal Convergence Factor for IIR Adaptive FiltersJuan E. Cousseau, Paulo S. R. Diniz. 137-140
- Application of the Piecewise Ellipsoidal Approximation Technique to Design CenteringLeszek J. Opalski, Jacek Wojciechowski. 137-140
- A New Blocking Scheme for Transform Coding of Multidimensional SignalsTsuhan Chen. 137-140
- Multi-Parameter Homotopy Methods for Finding Periodic Solutions of Nonlinear CircuitsDenise Wolf, Seth Sanders. 137-140
- Tree-Structure Architecture and VLSI Implementation for Vector Quantization AlgorithmsChung-Wei Ku, Liang-Gee Chen, Tzi-Dar Chiueh, Her-Ming Jong. 139-142
- Fault Tolerant Adaptive Filter Structure Based on the Generalized Subband Decomposition of FIR FiltersMariane R. Petraglia, Sanjit K. Mitra. 141-144
- Low-Power Time-to-digital and Digital-to-time Converters for Novel Implementation of Telecommunication Building BlocksTimo Rahkonen, Juha Kostamovaara. 141-144
- VAMP: A Hierarchical Framework for Design for ManufacturabilityMorie E. Malowany, Gordon W. Roberts, Vinod K. Agarwal. 141-144
- A 16x16-bit Static CMOS Wave-Pipelined MultiplierFabian Klass, Michael J. Flynn, A. J. van de Goor. 143-146
- On Multidimensional Linear Phase Perfect Reconstruction Filter BanksSankar Basu, Han-Mook Choi. 145-148
- Adaptive Control of Sampling Rate Using a Local Time-Domain Sampling TheoremPhilip E. Luft, Timo I. Laakso. 145-148
- Hybrid Multivariate Marginal Median FiltersKari-Pekka Estola, Risto Suoranta. 145-148
- A CAD Environment for Performance and Yield Driven Circuit Design Employing Electromagnetic Field SimulatorsJ. W. Bandler, R. M. Biernacki, S. H. Chen, P. A. Grobelny. 145-148
- Design and Characterization of an Integrated Optical Switch Driver CircuitP. Debie, R. Coppoolse, K. De Kesel, Peter Van Daele, J. Vandewege, L. Martens. 149-152
- A Fast Two-Dimensional Quasi-Newton Adaptive FilterJeffrey C. Strait, W. Kenneth Jenkins. 149-152
- Worst Case Design of Digital Integrated CircuitsJ. C. Zhang. 153-156
- Modular Approach for Analog VLSI Fuzzy Control Implementation and Piecewise Linear ApproximationJaime Ramírez-Angulo. 153-156
- Power Oscillator Design: Class EKim Fung Tsang, G. B. Morgan, P. C. L. Yip, Wing Shing Chan. 153-156
- Improved Methods for the Design of 1-D and 2-D QMF BanksHua Xu, Wu-Sheng Lu, Andreas Antoniou. 153-156
- Microstrip Implementation of Optimal Pulse Position Modulation Pre-detection FitlersRobert A. Cryan, A. Hussain, T. Hartley. 153-156
- A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev RecursionAn-Yeu Wu, K. J. Ray Liu. 155-158
- On the Design of Stabilizing Control for Structured Uncertain Singularly perturbed SystemsB. Bandyopadhyay, Jayalekshmi Nair, M. C. Srisailam. 157-160
- Generation of Signals in a Buck Converter with Sliding Mode ContolEnric Fossas, Josep M. Olm. 157-160
- A Floorplanner driven by Structural & Timing ConstraintsAbdelhakim Safir, Baher Haroun, Krishnaiyan Thulasiraman. 157-160
- Implementation and Performance Considerations for a PPM Correlator-synchroniserJaafar M. H. Elmirghani, Robert A. Cryan. 157-160
- Virtual Hardware and the Limits of Computational Speed-upOsama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke. 159-162
- Spectra of Graphs with Circulant Blocks and their ApplicationsJacek Wojciechowski, Jiri Vlach. 161-164
- A New Approach to Floorplan Area Optimization: To Slice or not to Slice?Cheng-Hsi Chen, Ioannis G. Tollis. 161-164
- Sign Haar TransformBogdan J. Falkowski, Susanto Rahardja. 161-164
- An Approach to Testability Improvement of Mixed-Signal BoardsJosé Silva Matos, João Canas Ferreira, Ana C. Leão, José Machado da Silva. 161-164
- A Fast Adaptive RAM-based Decision Feedback Equalizer for Partial-Response Nonlinear Recording ChannelsH. C. Hwang, C. H. Wei. 161-164
- Forum: Wave-pipelining: Is it Practical?Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski. 163-166
- Design and Simulation of Nonlinear Switched Capacitor Autonomous Circuits Containing Nonlinear Active ResistorXing Dong Jia, Richard M. M. Chen. 165-168
- A Floorplanning Method with Topological Constraint ManipulationTetsushi Koide, Yoshinori Katsura, Katsumi Yamatani, Shin ichi Wakabayashi, Noriyoshi Yoshida. 165-168
- Maximally Continuous WindowsMagdy T. Hanna. 165-168
- A Set of Youla s Equivalent Constraints on Broadband MatchingJin-Liang Wan, Wai-Kai Chen. 165-168
- Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching StrategyWen-Wei Yang, Li-Fu Jeng, Chen-Yi Lee. 165-168
- The Chip Design of A 32-b Logarithmic Number SystemSheng-Chieh Huang, Liang-Gee Chen, Thou-Ho Chen. 167-170
- Multirate Operations for Exact Interpolation and Iterative Subdivision SchemesCormac Herley. 169-172
- Interior Point Methods for PlacementP. Chin, Anthony Vannelli. 169-172
- Theory of Information Network - Properties of Minimum Response Time NetworkHitoshi Watanabe. 169-172
- Application Specific Memories for ATM Packet SwitchingAlex G. Dickinson, C. J. Nicol, S. K. Rao, M. Hatamian. 169-172
- HD and IMD Prediction Techniques for Active FiltersX. Zeng, P. Bowron, A. A. Muhieddine. 169-172
- On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor DesignWen-Zen Shen, Yi-Hsin Tao, Lan-Rong Dung. 171-174
- On Three-Way Graph PartitioningYoko Kamidoi, Shin ichi Wakabayashi, Noriyoshi Yoshida. 173-176
- Explicit Circuit Models of Multi-Dimensional Piecewise-Linear NetworksJaromír Brzobohaty, Jirí Pospísil, Stanislav Hanus. 173-176
- Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock SkewJosé Luis Neves, Eby G. Friedman. 175-178
- Fuzzy Partitioning applied to VLSI-Floorplanning and PlacementCarsten F. Ball, Peter V. Kraus, Dieter A. Mlynski. 177-180
- Design of Fuzzy Filters by Genetic AlgorithmsRiccardo Caponetto, Luigi Fortuna, C. Vinci. 177-180
- Model-Assisted Coding of Video Teleconferencing Sequences at Low Bit RatesAlexandros Eleftheriadis, Arnaud Jacquin. 177-180
- High Performance CMOS Macromodule Layout SynthesisJaewon Kim, Sung-Mo Kang, Sachin S. Sapatnekar. 179-182
- Twin-Chaos - Simultaneous Asynchronous Oscillations of ChaosKatsunori Suzuki, Yoshifumi Nishio, Shinsaku Mori. 181-184
- Efficient Algorithms for Two and Three-Layer Over-the-Cell Channel RoutingPaul-Waie Shew, Jin-Tai Yan, Pei-Yung Hsiao, Yong Ching Lim. 183-186
- Exact Reconstruction Filter Banks Using Cosine Modulation: Matrix Formalization for Arbitrary Length Prototype FiltersChristine Guillemot, Patrice Onno. 185-188
- Training Recursive Structures for Weighted Order Statistic FilteringLori Lucke, Randall A. Kroenke. 185-188
- The Generalized Bilinear System: a Class of Nonlinear Discrete SystemsTamal Bose, Kyung Sub Joo. 185-188
- A New Approach of Fractional-Dimension Based Module Clustering for VLSI LayoutMasahiko Toyonaga, Shih-Tsung Yang, Toshiro Akino, Isao Shirakawa. 185-188
- An Efficient Four Layer Over-the-Cell RouterSreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam. 187-190
- Distortion Compensation of Multi-Mesfet CircuitsD. R. Webster, David G. Haigh, Anthony E. Parker. 189-192
- Context-Dependent Modeling in Alphabet RecognitionPhilipos C. Loizou, Andreas Spanias. 189-192
- On Estimation of Nonlinear Systems by Nonparametric TechniquesAdam Krzyzak, Rolf Unbehauen. 189-192
- Automatic Functional Cell Generation in the Sea-of-Gates Layout StyleYhonkyong Choi, Juhyun Lee, Chong S. Rim. 189-192
- Comparative Analysis of New CMOS Leaf Cells for OTC RoutingPramod Anne, Aditya Reddy, Naveed A. Sherwani, Anand Panyam, Siddharth Bhingarde. 191-194
- Iterative Signal Extrapolation Algorithms with WaveletsLi-Chien Lin, C. C. Jay Kuo. 193-196
- Development of a Cinfinty-Continuous Small-Signal Model for a MOS TransistorBenjamín Iñíguez, Eugenio García Moreno. 193-196
- A Maximum Clique Derivation Algorithm for Simplification of Incompletely Specified MachinesMasaki Hashizume, Takeomi Tamesada, Akio Sakamoto. 193-196
- Logic Value Assignment Contribution to Testability AnalysisH. J. Kadim, G. E. Taylor. 195-198
- Efficient Algorithms for the Calculation of Arithmetic Spectrum from OBDD & Synthesis of OBDD from Arithmetic Spectrum for Incompletely Specified Boolean FunctionsBogdan J. Falkowski, Chip-Hong Chang. 197-200
- The Optimisation of Multiplier-Free Directed Graphs: an Approach using Genetic AlgorithmsDavid R. Bull, Alexis Aladjidi. 197-200
- On the Geometrical Structure of Network EquationsSteffen Paul, Knut Hüper, Josef A. Nossek. 197-200
- Improving the Testability of VLSI Circuits through PartitioningSami A. Al-Arian, Randy E. Bolling. 199-202
- A Realization Method of the Transfer Functions Containing Variable ParameterAtsushi Kawakami. 201-204
- Error Accumulation of Repetitive Image CodingShih-Fu Chang, Alexandros Eleftheriadis. 201-204
- Cupland - A Behavioral Level Description Compiler for Designing of PLD/EPLD-Based SystemsStanislaw Deniziak, Krzysztof Sapiecha. 201-204
- The PBF of One Weight Weighted Median FiltersTong Sun, Moncef Gabbouj, Yrjö Neuvo. 201-204
- VLSI Architectures for Computing Exponentiations, Multiplicative Inverses, and Divisions in GF(2:::m:::)Shyue-Win Wei. 203-206
- A Semi-Analytical Procedure to Describe Lossless Two-Ports with Mixed Lumped and Distributed ElementsAhmet Aksen, B. Siddik Yarman. 205-208
- The Wavelet Scalar Quantization Compression Standard for Digital Fingerprint ImagesJonathan N. Bradley, Christopher M. Brislawn. 205-208
- A Robustness Approach to Envelope-Constrained FilteringWei Xing Zheng, Antonio Cantoni, Kok Lay Teo. 205-208
- On the Synchronization of Oscillators Coupled by One Negative ResistorHiroyuki Kanasugi, Seiichiro Moro, Yoshifumi Nishio, Shinsaku Mori. 205-208
- Scheduling of Signal Transition Graphs under Timing ConstraintsUwe F. Baake, Sorin A. Huss. 205-208
- A Digit-Serial Architecture for Gray-Scale Morphological FilteringLori Lucke, Chaitali Chakrabarti. 207-210
- Parametric Analysis of Weighted Order Statistic FiltersRuikang Yang, Moncef Gabbouj, Pao-Ta Yu. 209-212
- A Test Structurefor Extraction of Resistance Matching PropertiesFrode Larsen, Mohammed Ismail, Ali Iranmanesh. 209-212
- A Fast Array Architecture for Block Matching AlgorithmJongSeob Baek, Seunghyun Nam, Moonkey Lee, Chuldong Oh, Kisoo Hwang. 211-214
- Motion Compensated Video Compression and Dense Motion Field CodingNavid Haddadi, C. C. Jay Kuo. 213-216
- Synchronization Phenomena in RC Oscillators Coupled by One ResistorSeiichiro Moro, Yoshifumi Nishio, Shinsaku Mori. 213-216
- A Linear Time Algorithm for Timing Directed Circuit OptimizationsSanjive Agarwala, Patrick W. Bosshart. 213-216
- Compact and Accurate MOST Model for Analog Circuit Hand CalculationsFarbod Aram, Aria Eshraghi, Terri S. Fiez. 213-216
- VLSI Architectures for Hierarchical Block MatchingGagan Gupta, Chaitali Chakrabarti. 215-218
- Exploring Delay/Area Trade-Offs of an LDI Filter Using a Natural Based AlgorithmChris J. Rousse, Alison J. Carter. 217-220
- Principles of nonlinearity Cancellation in Linear MOS Systems using MRC CircuitsZdzislaw Czarnul, Shigetaka Takagi, Nobuo Fujii, Tetsuya Iida, Takeshi Yanagisawa. 217-220
- Video Motion Estimation Using a Neural NetworkS. S. Skrzypkowiak, Vijay K. Jain. 217-220
- Single-Layer CNN SimulatorChi-Chien Lee, José Pineda de Gyvez. 217-220
- Design of Optimum Totally Perfect Connection-Blocks of FPGAKunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu. 221-224
- A Pipelined Systolic Arrays Architecture for the Hierarchical Block-Matching AlgorithmHyung Chul Kim, Seung Ryoul Maeng. 221-224
- Optimal Order for Signal and System ModelingAndreas Poncet, George S. Moschytz. 221-224
- Perturbations of CNNsMark P. Joy, Vedat Tavsanoglu. 221-224
- Optimization of Real-Time VLSI Architectures for Distributed Arithmetic-Based Algorithms: Application to HDTV FiltersKamal Nourji, Nicolas Demassieux. 223-226
- Stereo Correspondence with Discrete-Time Cellular Neural NetworksSungjun Park, Seung-Jai Min, Soo-Ik Chae. 225-228
- Further Generalization of Higher Order Elements: State Characterization and SynthesisLiviu Goras, Adrian Leuciuc. 225-228
- A Systolic Graph Partitioning Algorithm for VLSI DesignShin ichi Wakabayashi, Kazunori Isomoto, Tetsushi Koide, Noriyoshi Yoshida. 225-228
- A Weighted Lattice Structure for 2-D Denominator-Separable Digital FiltersXiaoning Nie, Rolf Unbehauen. 225-228
- Training of Artificial Neural Network for Tomographic Reconstruction of Time Varying ObjectYing Ha Chiu, Sze-Fong Yau. 225-228
- Partitioning and Retiming of Multi-Dimensional SystemsNelson L. Passos, Edwin Hsing-Mean Sha, Steven C. Bass. 227-230
- Behavioral Testing of Cellular Neural NetworksJohn Willis, José Pineda de Gyvez. 229-232
- Synthesis of Customized Hardware from ADAMichael Dossis, James M. Noras, Gary J. Porter. 229-232
- Research on Stepsize Control in the BDF Method for Solving Differential Algebraic EquationsM. Zhuang, Wolfgang Mathis. 229-232
- Lost Motion Vector Recovery AlgorithmChoon Soo Park, Jongchul Ye, Sang Uk Lee. 229-232
- A Robust Quasi-Newton Adaptive Filtering AlgorithmMarcello L. R. de Campos, Andreas Antoniou. 229-232
- Multi-Threaded Processor for Image GenerationTakayuki Sagishima, Kozo Kimura, Hiroaki Hirata, Tokuzo Kiyohara, Shigeo Asahara, Takao Onoye, Isao Shirakawa. 231-234
- A New Efficient 2-D LMS Adaptive Filtering AlgorithmSau-Gee Chen, Yung-An Kao. 233-236
- Probabilistic Fault Diagnosis in Communications ArchitecturesJohn Narraway. 233-236
- NEAT: An Object Oriented High-Level Synthesis InterfaceM. J. M. Heijiligers, H. A. Hilderink, Adwin H. Timmer, Jochen A. G. Jess. 233-236
- On non-Linear Multi-FET AnalysisCarlos A. Losada, David G. Haigh. 233-236
- An Analog Radial Basis Function Circuit Using a Compact Euclidean Distance CalculatorS. Collins, G. F. Marshall, D. R. Brown. 233-236
- A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley TransformJiun-In Guo, Chi-Min Liu, Chein-Wei Jen. 235-238
- A Single Chip Implementation of Receive Path Termination for SONET OC-12c and Quadruple SONET OC-3cSrini W. Seetharam, Gary J. Minden, Joseph B. Evans. 237-240
- Fast Convergence with Low Precision Weights in ART1 NetworksJean-Francois Crespo, Pierre Lavoie, Yvon Savaria. 237-240
- DC Analysis of Networks Containing Ideal Diodes, using the Decomposed State Model of a One-Dimensional Piecewise-Linear SystemJaromír Brzobohaty, Jirí Pospísil, Zdenek Kolka. 237-240
- A High Performance FPGA with Hierarchical Interconnection StructurePing-Tsung Wang, Kun-Nen Chen, Yen-Tai Lai. 239-242
- On Absolute Stability of Neural NetworksM. Forti, A. Liberatore, Stefano Manetti, Mauro Marini. 241-244
- A 2:::1:::/::2::-Dimensional Systolic Array ArchitectureStephen P. S. Lam. 243-246
- New Results on Stability Theory of Time-Varying Linear SystemsJinhui Chao, Teruyuki Sato, Kohichi Sakaniwa, Shigeo Tsujii. 245-248
- Exact Data Retrieval of Associative Memory with Further Reduced Cross TalkYukio Kumagai. 245-248
- An Estimation of Time-Varying Parameters using Multi-AR Lattice Models in SubbandsJun ya Shimizu, Yoshikazu Miyanaga, Koji Tochinai. 245-248
- A Pipelined Architecture to Map ATM Cells to 622 Mb/s SONET OC-12 PayloadsSrini W. Seetharam, Gary J. Minden, Joseph B. Evans. 245-248
- Modeling Cell Processing Hardware with Action DiagramsKarim Khordoc, Eduard Cerny. 245-248
- Synthesis of Fault Tolerant Architectures for Molecular DynamicsShalini Yajnik, Niraj K. Jha. 247-250
- Estimating Performance Characteristics of Loop TransformationsMinjoong Rim, Rajiv Jain. 249-252
- A New Cost Function Allowing Parallel Processing of Adaptive FiltersYoji Yamada, Shigenori Kinjo, Hiroshi Ochi. 249-252
- Boundary Matching Detection for Progressive Transmission of VQ Indices over Noisy ChannelsW. J. Zeng, Y. F. Huang. 249-252
- Neural Network Control of FES in Paraplegics for Patient-Responsive AmbulationDaniel Graupe, Hubert Kordylewski. 249-252
- Computer Formulation of Averaged Models for Periodically-Switched NetworksWilliam Y. M. Lai, C. K. Tse, C. H. Szeto. 253-256
- Asynchronus Implementation for the Add Compare Select Processor for Communication SystemsAria Eshraghi, Terri S. Fiez, Thomas R. Fischer. 253-256
- Multilayer Neural Network Structures as Volterra FilterStanislaw Osowski, Than Vu Quang. 253-256
- Effect of the Transistor Mismatches on the Performance of Fully-Differential OTASJosé Silva-Martínez. 253-256
- Application of Adaptive CPWL Filter in Impulsive Noise RemovalJi-Nan Lin, Rolf Unbehauen. 253-256
- Multipurpose Chip for Physiological MeasurementsMaini Williams, Jari Nurmi. 255-258
- A Decoding Strategy Using Graph Partitioning for Continuous-Speech RecognitionJohn R. Deller Jr., C.-C. Chiu, Y. P. Yang. 257-260
- Graphical Specification Methods for Digital Telecommuniation ASICsJukka Lahti. 257-260
- Feedback Cancellation in Hearing Aids: Results from using Frequency-Domain Adaptive FiltersPius Estermann, August Kaelin. 257-260
- Pattern Recognition and System Control with a Neural ProcessorJames Donald, Lex A. Akers. 257-260
- A Novel Bit-Serial Design of Comb Filters for Oversampling A/D ConvertersNianxiong Tan, Sven Eriksson, Lars Wanhammar. 259-262
- On a New Predictor for the Waveform Coding of Speech Signal by Using the Dual Autocorrelation and the Sigma Delta TechniqueMyungJin Bae, DaeSik Kim, HongYeol Jeon, SouGuil Ann. 261-264
- An Image Binarization and Reconstruction with Resistive NetworkYasutami Chigusa, Kensuke Suzuki, Mamoru Tanaka. 261-264
- A Novel Method for Discrete Coefficient FIR Digital Filter DesignTolga Çiloglu, Zafer Ünver. 261-264
- An FFT-Based Fault Tolerant FIR Adaptive FilterBernard A. Schnaufer, W. Kenneth Jenkins. 261-264
- Use of Multiplier Blocks to Reduce Filter ComplexityAndrew G. Dempster, Malcolm D. Macleod. 263-266
- Adaptive RBF Neural Network in Signal DetectionWahid Ahmed, Donald M. Hummels, Mohamad T. Musavi. 265-268
- Variable Step-Size LMS Algorithm: New Developments and ExperimentsBehrouz Farhang-Boroujeny. 265-268
- An Overall FIR Filter Optimization Tool for High Granularity Implementation TechnologiesJouni Isoaho, Jari Nurmi. 265-268
- Canonical Realisation of Ladder Based Transconductor-capacitor FiltersLu Yue, John I. Sewell, N. P. J. Greer. 265-268
- 3-D Subband Video Coding Technique Using Adaptive Wavelet Packet BasesYong Kwan Kim, Sang Uk Lee. 265-268
- VLSI Array Processors Implementation of Block-State IIR Digital FiltentrsA. Tawfik, Fayez El Guibaly, Panajotis Agathoklis. 267-270
- Neural Networks for Optimization Problems in Graph TheoryJenn-Shiang Lai, Sy-Yen Kuo, Ing-Yi Chen. 269-272
- Frequency and Phase Tuning of Continuous-Time Integrated Filters using Common-Mode SignalsAdam Wyszynski, Rolf Schaumann. 269-272
- Filters Derived from the Addtion or Subtraction of Two m-D All-Pass FiltersVenkat Ramachandran, Majid Ahmadi, Christian S. Gargour. 269-272
- Mixed Analog-Digital Simulation: The tools are here... is anyone really using them?John Harris, Mark Chadwick, Tom Quan, Norbert Diesing, Edward MacRobbie. 269-274
- A Fast DCT Processor, Based on Special Purpose CORDIC RotatorsEvaggelinos P. Mariatos, D. E. Metafas, John Ant. Hallas, Constantinos E. Goutis. 271-274
- Symmetric Extension Methods for Parallel M-Channel PR LP FIR Analysis/Synthesis SystemsLi Chen, Truong Q. Nguyen, Kwok Ping Chan. 273-276
- Four-Quadrant CMOS/BiCMOS Multipliers Using Linear-Region MOS TransistorsChristopher J. Abel, Satoshi Sakurai, Frode Larsen, Mohammed Ismail. 273-276
- A Homotopy Continuation Method for Parameter Estimation in MRF Models and Image RestorationP. K. Nanda, Uday B. Desai, P. G. Poonacha. 273-276
- A New Non Competitive Unsupervised Neural Network for ClusteringGiuseppe Acciani, Ernesto Chiarantoni, M. Minenna. 273-276
- Fast Spectrum Computation for Logic Functions using Binary Decision DiagramsMasahiro Fujita, Jerry Chih-Yuan Yang, Edmund M. Clarke, Xudong Zhao, Patrick C. McGeer. 275-278
- A 60-MBaud Single-Chip QAM-Processor for the Complete Base-Band Signal Processing of QAM DemodulatorsErik De Man, Matthias Schöbinger, Tobias G. Noll, Georg Sebald. 275-278
- Design of Motion Compensation Filters for Frequency Scalable Coding - Drift ReductionMasahiro Iwahashi, Koichi Ohyama, Wataru Kameyama, Noriyoshi Kambayashi. 277-280
- A Temporal Neural SystemJay Heeb, Lex A. Akers. 277-280
- Generalized Linear-Phase Lapped Orthogonal Transforms277-280
- A Novel Transconductance Block Eliminates the Need for Common-Mode Feedback in Fully Differential CircuitsPaul D. Walker, Michael M. Green. 277-280
- Using Binary Decision Diagrams to Speed up the Test Pattern Generation of Behavioral Circuit Descriptions Written in Hardware Description LanguagesLoïc Vandeventer, Jean François Santucci. 279-282
- Current Mode Techniques for Multiple Valued Arithmetic and LogicC. T. Clark, Graham R. Nudd, S. Summerfield. 279-282
- A Fast Learning Algorithm for Gabor Transform ExtractionAyman E. Ibrahim, Mahmood R. Azimi-Sadjadi, Sassan Sheedvash. 281-284
- Extraction of Depth Information by Cellular Neural NetworksMamoru Tanaka, Miotsuhiko Awata. 281-284
- On Generalization of Order Statistics Based FiltersJi-Nan Lin, Rolf Unbehauen. 281-284
- Avoiding Common-Mode Feedback in Continuous-Time Gm-C Filters by Use of Lossy IntegratorsAdam Wyszynski, Rolf Schaumann. 281-284
- Synthesis of Current Mode Building Blocks for Fuzzy Logic Control CircuitsMarek J. Patyra, John E. Long. 283-286
- Retiming and Clock Skew for Synchronous SystemsLiang-Fang Chao, Edwin Hsing-Mean Sha. 283-286
- Low Distortion Interfaces and Anti-alias Filters for Switched Current ApplicationsRichard A. H. Balmford, William Redman-White, J. B. Hughes. 285-288
- Analogue and Digital Neural VLSI: Duet or Duel?Alan F. Murray, Igor Aleksander, Andreas G. Andreou, Misha Mahowald. 285-288
- Biorthonormal Filter Banks and the Theory of Transfer Matrix InversionP. P. Vaidyanathan. 285-288
- Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller FormsChien-Chung Tsai, Malgorzata Marek-Sadowska. 287-290
- A Switched-Current Sigma Delta Converter for Direct Photodiode InterfacingM. Bracey, William Redman-White, J. B. Hughes. 287-290
- Cellular Neural Networks: the Analogic Microprocessor?Martin Hasler, Leon O. Chua, Josef A. Nossek, Ángel Rodríguez-Vázquez, Tamás Roska, Joos Vandewalle. 289-294
- Data-Dependent Alpha-Trimmed Mean Fitlers for Image RestorationAkira Taguchi. 289-292
- A Synthesis Framework Based on Trace and Automata TheoryJérôme Fron, Jerry Chih-Yuan Yang, Maurizio Damiani, Giovanni De Micheli. 291-294
- The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. LogicMarc Renaudin, Bachar El Hassan. 291-294
- A Switched-Current Double Sampling Bilinear Z-Transform Filter TechniqueJohn B. Hughes, Kenneth W. Moulding. 293-296
- Infinite Precision Analysis of the Fast QR Decomposition RLS AlgorithmMarcio G. Siqueira, Paulo S. R. Diniz, Abeer A. Alwan. 293-296
- A Novel Edge Detector Based on Nonlinear Local OperationsGeorge Economou, Spiros Fotopoulos, M. Vemis. 293-296
- General Modular Multiplication by Block Multiplication and Table LookupCheng-Wen Wu, Yung-Fa Chou. 295-298
- Improved Lower Bounds for the Scheduling Optimization ProblemYuan Hu, Bradley S. Carlson. 295-298
- Searching over DOA Parameter Space via Neural NetworksSheng Lin, Qin-Ye Yin. 295-298
- Trading Off Sspeed Versus Dynamic Range in Switched Current CircuitsPeter Shah, Chris Toumazou. 297-300
- Constrained Image Representation Using Multi-TransformsWasfy B. Mikhael, Arun Ramaswamy. 297-300
- Fast Design Algorithms for FIR Notch FiltersMiroslav Vlcek, Ladislav Jires. 297-300
- A Pulse Coded Winner-Take-All CircuitJack L. Meador, Paul Hylander. 299-302
- A Two-Stage Neural Network DC Fault DictionaryJerzy Rutkowski. 299-302
- Detecting hard faults with combined approximate forward/backward symbolic techniquesGianpiero Cabodi, Paolo Camurati, Stefano Quer. 299-302
- Two-Type-Interlaced Structure and LBR Test Applied to the Conventional Filter RealizationIl-Taek Lim, Byeong Gi Lee. 301-304
- High Speed Analog Filtering Using Feedforward Neural Network ArchitecturesYiren Chu, Iuri Mehr, Terry Sculley. 303-306
- An Approach for UIO Generation for FSM Verification and ValidationD. Schin, Yinan N. Shen, Fabrizio Lombardi. 303-306
- Efficient and Robust Test Generation-Based Timing AnalysisJoão P. Marques Silva, Karem A. Sakallah. 303-306
- A Low Voltage Wave SI Filter Implementation using Improved Delay ElementsBengt Jonsson, Sven Eriksson. 305-308
- Direct Synthesis of Efficient Speed-Independent Circuits from Deterministic Signal Transition GraphsSung Tae Jung, Chu Shik Jhon. 307-310
- A Dual Basis Systolic Divider for GF(2:::m:::)Sebastian T. J. Fenn, David Taylor, Mohammed Benaissa. 307-310
- Neural Networks for Quaternion-valued Function ApproximationPaolo Arena, Luigi Fortuna, Luigi Occhipinti, Maria Gabriella Xibilia. 307-310
- Switched-Current Ladder Band-Pas FiltersAntônio Carlos M. de Queiroz, Paulo R. Melo Pinheiro. 309-312
- An Analog MOS Model for Circuit Simulation and Benchmark Test ResultsRobert C.-H. Chang, Bing J. Sheu. 311-314
- Shortest Path Searching for the Robot Walking Using an Analog Resistive NetworkMitsuhisa Kanaya, Gui-Xin Cheng, Kouichiro Watanabe, Mamoru Tanaka. 311-314
- A Fast Radix-4 Division AlgorithmHosahalli R. Srinivas, Keshab K. Parhi. 311-314
- An Extended Overlap-Add Method and -Save Method for Sampling Rate ConversionShogo Muramatsu, Hitoshi Kiya. 313-316
- Floating Gate Charge-Sharing: a Novel Circuit for Analog TrimmingWeinan Gao, W. Martin Snelgrove. 315-318
- Modeling Symmetry in Analog Electronic CircuitsM. E. Kole, J. Smith, O. E. Herrmann. 315-318
- A Study of the Sensitivity of Switched-Current Wave Analog Filters to Mismatching and Clock-Feedthrough ErrorsAlberto Yufera, Adoración Rueda, José L. Huertas. 317-320
- GODPE: Global Optimization in Small Signal Device Model Parameter ExtractionDongfeng Zhao, Ray R. Chen. 319-322
- A Recurrent Neural Network for Solving the Shortest Path ProblemJun Wang. 319-322
- A Multibit Delta-Sigma D/A Converter Using a Charge Integrating Sub-ConverterDaejong Kim, Jaejin Park, Sungjoon Kim, Deog Kyoon Jeong, Wonchan Kim. 319-322
- On the Synthesis of Optimal Stack Filters under Structural ConstraintsLin Yin. 321-324
- Switched-Current Multirate FilteringWang Ping, José E. Franca. 321-324
- On the Modelling of a CMOS Magnetic SensorJack Lau, Ping K. Ko, Philip C. Chan. 323-326
- Handwritten Numeral Recognition with Multiple Features andd Multistage ClassifiersJun Cao, Majid Ahmadi, Malayappan Shridhar. 323-326
- An Alorithmic Analog-to-Digital Converter with low Ratio-and Gain-Sensitivities and 4N-Clock Conversion CycleShu-Yuan Chin, Chung-Yu Wu. 325-328
- A VDMOS transistor model taking into account the thermoelectrical interactionsChristophe Lallement, R. Bouchakour, T. Maurel. 327-330
- Character Recognition by Neural Networks with Single-Layer Training and Rejection MechanismJoonho Lim, Eel-Wan Lee, Soo-Ik Chae. 327-330
- Simulating Nonuniform Lossy Lines with Frequency Dependent Parameters by the Method of CharacteristicsAli El-Zein, Monjurul Haque, Salim Chowdhury. 327-330
- On the Formal Derivaiton of a Systolic Array for Recursive Least Squares EstimationIan K. Proudler, John G. McWhirter, Marc Moonen. 329-332
- A Radical-Partitioned Neural Network System Using a Modified Sigmoid Function and a Wight-Dotted Radical Selector for Large-Volume Chinese Characters Recognition VLSIJames B. Kuo, B. Y. Chen, Mark W. Mao. 331-334
- Transient Simulation of Nonuniform Transmission Lines by Asymptotic Waveform EvaluationMonjurul Haque, Ali El-Zein, Salim Chowdhury. 331-334
- Graceful Degradation in Algorithm-Based Fault Tolerant Multiprocessor SystemsShalini Yajnik, Niraj K. Jha. 333-336
- Quantiser Gain in Nth-Order Sigma-Delta Modulator Linear Models: Its Determination Based on Constant Output Power CriterionPaul T. Maguire, Qiuting Huang. 333-336
- PNS Modules for the Synthesis of Parallel Self-Organizing Hierarchical Neural NetworksFaramarz Valafar, Okan K. Ersoy. 335-338
- Current Input TSPC Latch for High Speed, Complex Switching TreesP. Zhou, J. C. Czilli, Graham A. Jullien, William C. Miller. 335-338
- Macromodel Simplification Using Dimensional AnalysisAyman I. Kayssi, Karem A. Sakallah. 335-338
- Effects of Quantiation noise in Parallel Arrays of Analog-to-Digital ConvertersAntonio Petraglia, Marcos Aurélio de Andrade Pinheiro. 337-340
- A Conceptual Associative Memory with Full Memory Capacity and Ability to Associate Arbitrary PatternsCheng-Juei Wu. 339-342
- Accurate Modelling of the Non-Linear Settling Behaviour of Current Memory CircuitsNicolas Moenclaey, Andreas Kaiser. 339-342
- Adaptive Photoreceptor with Wide Dynamic RangeTobi Delbrück, Carver Mead. 339-342
- Error Analysis of Parallel Analog to Digital ConvertersJorge R. Fernandes, Manuel M. Silva. 341-344
- A Fast Low-Power Driver for Long Interconnections in VLSI SystemsMohamed Nekili, Yvon Savaria, Guy Bois. 343-346
- A Multilayer Feedforward Neural Network Model for Digital Hardware ImplementationHon Keung Kwan, Chuan Zhang Tang. 343-346
- Modeling of Frequency-dependent Hysteresis with SPICEHans Georg Brachtendorf, Rainer Laur. 343-346
- High-Linearity Calibration of Low-Resolution Digital-to-Analog ConvertersJoão Goes, José E. Franca, Nuno F. Paulino, J. Grilo, Gabor C. Temes. 345-348
- Filter-Bank Interpretation and Fixed-Point Numerical Accuracy of Subband FFTUlrich Heute, Abdulnasir Hossen. 345-348
- A Novel Method for the Fault Detection of Analog Integrated CircuitsZhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen. 347-350
- A Comparative Study of Single-Phase Clocked Latches Using Estimation CriteriaSameh Ghannoum, Dmitri Chtchvyrkov, Yvon Savaria. 347-350
- Analog VLSI Chip for StereocorrespondenceMisha Mahowald. 347-350
- On the Stability and Configuration of Sigma Data ModulatorsG. Ushaw, Steve McLaughlin. 349-352
- Analog Fault Diagnosis - A Practical ApproachSalman Ahmed, Peter Y. K. Cheung. 351-354
- A Novel Reduced Swing CMOS Bus Interface Circuit for High Speed Low Power VLSI SystemsReza Golshan, Baher Haroun. 351-354
- A Bandpass Subsampled Delta-Sigma Modulator for Narrowband Cellular Mobile CommunicationsFrédéric Gourgue, Maurice G. Bellanger, Sabrina Azrouf, Vincent Bruneau. 353-356
- Low Power CMOS Clock BufferKei-Yong Khoo, Alan N. Willson Jr.. 355-358
- A CMOS Current-Mode PWM Technique for Analog Neural Network ImplementationsHong-Kui Yang, Ezz I. El-Masry. 355-358
- Combining Subband Decomposition and Sigma Delta Modulation for Wideband A/D ConversionRonald F. Cormier Jr., Terry L. Sculley, Roberto H. Bamberger. 357-360
- Novel Design for Binary to RNS ConvertersP. V. Ananda Mohan. 357-360
- A Fast CMOS Voltage-Controlled Ring OscillatorYvon Savaria, Dmitri Chtchvyrkov, John F. Currie. 359-362
- Analog Cellular Neural Network with Application to Artial Differential Equations with Variable Mesh-SizeD. Gobovic, Mona E. Zaghloul. 359-362
- Towards Expandable and Generalised Analogue Design AutomationK. K. Wee, R. J. Mack. 359-362
- Circuit Implementation of a Nonmonotone Activation FunctionIulian B. Ciocoiu. 363-366
- Building Blocks for a Temperature-Compensated Analog VLSI Neural Network with On-Chip LearningAntonio J. Montalvo, Ronald S. Gyurcsik, John J. Paulos. 363-366
- Sensitivity-Driven Placement of Analog ModulesRonald S. Gyurcsik, George Gad-El-Karim, Griff L. Bilbro. 363-366
- Stability Analysis of the Second Order Sigma-Delta ModulatorPhilip Steiner, Woodward Yang. 365-368
- Computation of the Time-Frequency Q-Distribution of AltesTomasz P. Zielinski. 365-368
- Analogue CMOS VLSI Implementation of Cellular Neural Networks with Continuously Programmable TemplatesPeter R. Kinget, Michiel Steyaert. 367-370
- A Fuzzy-logic based Tool for Topology Selection in Analog SynthesisJorge Chávez Orzáez, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo. 367-370
- A New Block Adaptive Algorithm Using Order Recursive UD Factorization MethodToshihiro Furukawa, Sadanobu Yoshimoto, Hajime Kubota. 369-372
- A 12 Bit, 2V Current-Mode Pipelined A/D Converter NonlinearityLigang Zhang, Terry L. Sculley, Terri S. Fiez. 369-372
- Subthreshold Analog Circuit for Computing the Maximum Principal Component of 3-D DataShanti S. Vedula, Fathi M. A. Salam, Gamze Erten. 371-374
- A Methodology for Automatic Generation of Data Conversion Topologies from AlgorithmsN. C. Horta, José E. Franca. 371-374
- Frequency-Domain Analysis of A/D Converter NonlinearityZhiqiang Gu, W. Martin Snelgrove. 373-376
- Analog Design optimization by means of a Tabu Search ApproachMiguel Angel Aguirre Echánove, Jorge Chávez Orzáez, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo. 375-378
- Pulse Stream VLSI Neural Systems: Into RoboticsGeoffrey B. Jackson, Alister Hamilton, Alan F. Murray. 375-378
- A Fast Convergence Median LMS AlgorithmK. F. Wan, P. C. Ching. 377-380
- Digitally-Controlled Analogue Signal Processing and Conversion Techniques Employing a Logarithmic Building BlockJorge Guilherme, José E. Franca. 377-380
- Improving AWE Accuracy Using Multipoint Padé ApproximationMustafa Celik, O. Ocali, Mehmet Ali Tan, Abdullah Atalar. 379-382
- CMOS Design of Two Winner-Take-All Circuits Using Pulse Duty Cycle Synaptic WeightingG. Moon, Mona E. Zaghloul, R. W. Newcomb. 379-382
- An Oversampled Modulator for A/D Conversion with Minimized Analog ContentCarlos Azeredo Leme, Piero Malcovati, Henry Baltes. 381-384
- A New Variable Step-size Algorithm using Genetic-Type SearchShu Hung Leung, C. Y. Chung, Sin Chun Ng. 381-384
- Compact Modelling in Circuit Simulation: the General Purpose Analyser OPTIMA-3Jan Ogrodzki, Dariusz Bukat. 383-386
- On Multiple Transition Branch Hidden Markov ModelsXixian Chen, Xiaoming Ma, Lie Zhang, Shanpei Wu, Shilei Liu. 385-388
- A Class of Order Statistics Learning Vector QuantizersIoannis Pitas, Constantine Kotropoulos, Nikos Nikolaidis, Ruikang Yang, Moncef Gabbouj. 387-390
- Efficient DOA Estimation by a Specific SVD AlgorithmA. Massetani, Francesco Piazza, Aurelio Uncini. 389-392
- A Novel Consistent MOSFET Model for CAD Application with Reduced Calculation TimeMichiko Miura-Mattausch, Alexander Rahm, Michael Bollu, Ute Feldmann, Dominique Savignac. 391-394
- Using Noise-Feedback in Approximating ML Sequence Estimation for Channels with Infinite Intersymbol InterferenceThomas Ernst, August Kaelin. 393-396
- Systematic Generation of Current-Mode Second Order RC OscillatorsDan Stiurca. 393-396
- Performance Analysis of Hopfield Neural Networks for DOA EstimationSheng Lin, Qin-Ye Yin. 395-398
- Transistor-Level Consideration of an RC Current-Mode Oscillator using Unity-Gain Current-MirrorsSitthichai Pookaiyaudom, Jitkasem Ngarmnil. 397-400
- Arabitrarily Shaped Cell Placement by Three-Layer Self-Organizing Neural NetworksRay-I Chang, Pei-Yung Hsiao. 399-402
- An Integrated Modelling Technique for Hardware/Software SystemsErik Stoy, Zebo Peng. 399-402
- High Frequency Performance of Current-Mode Precision Full Wave RectifiersKhaled Hayatleh, S. Porta, F. J. Lidgey. 401-404
- Bayesian procedure for the Detection of Damped SignalsPetar M. Djuric, William B. Bishop, Douglas E. Johnston. 401-404
- Minimal Training Set Size Estimation for Neural Network-Based Function ApproximationAleksander Malinowski, Jacek M. Zurada, Peter B. Aronhime. 403-406
- An Analogue Current-Mode Signal Processing ASIC for Interrogating Resistive Sensor ArraysPhilip I. Neaves, John V. Hatfield. 405-408
- A Technique to Improve Convergence Speed of the LMS AlgorithmKiyoshi Nishikawa, Hitoshi Kiya. 405-408
- A Graph-Theoretic Approach to Clock Skew OptimizationRahul B. Deokar, Sachin S. Sapatnekar. 407-410
- Time-Mulitplexing CNN SimulatorChi-Chien Lee, José Pineda de Gyvez. 407-410
- DC Offset Performance of Four LMS Adaptive AlgorithmsAyal Shoval, David A. Johns, W. Martin Snelgrove. 409-412
- A Current-Mode FDNR Circuit Element using Capacitive GyratorsVladimir I. Prodanov, Michael M. Green. 409-412
- Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor CircuitsMasaki Ishida, Koichi Hayashi, Masakatsu Nishigaki, Hideki Asai. 411-414
- Structural Pattern Compression and Recognition by Linear CNNGui-Xin Cheng, Mamoru Tanaka. 411-414
- Design of the Wilson and Improved Wilson MOS Current Mirrors to Reach the Best Settling timeGaetano Palumbo. 413-416
- Some Thoughts on Least Squared Error Optimal WindowsRamesh A. Gopinath. 413-416
- Concurrent Switch-Level Timing Simulation Based on Waveform RelaxationBengt-Arne Molin, Sven Mattisson. 415-418
- A 16-Bit Current Sample/Hold Circuit Using a Digital CMOS ProcessIuri Mehr, Terry Sculley. 417-420
- Computationally-improved Optimal Filtering for Supervised LearningSaida Benromdhane, Fathi M. A. Salam. 419-422
- Transient Simulation of Coupled Lossy Interconnects by Window Partitioning TechniqueVijaya Gopal Bandi, Hideki Asai. 419-422
- Interval Finite-Difference Methods for Digital MOS Circuits SimulationYing-Wen Bai. 423-426
- Search of Optimal Solutions in Multi-Level Neural NetworksSa Hyun Bang, Bing J. Sheu, Josephine C.-F. Chang. 423-426
- Interlaced Sampling for Noise ReductionV. Uhlemann, Bedrich J. Hosticka, W. Brockherde. 425-428
- A New Approach to Nonlinear Digital Signal ProcessingDouglas Frey. 425-428
- Certain Facts about Kohonen s LVQ1 AlgorithmClaudia Diamantini, Arnaldo Spalvieri. 427-430
- Lattice Wave Digital Filter Design for Arbitrarily Specified Amplitude Characteristics by Phase ApproximationIbrahim Fathy Tarrad, Tamás Henk. 429-432
- A Discriminative Training Algorithm for Predictive Neural Network ModelsKyungMin Na, JaeYeol Rheem, SouGuil Ann. 431-434
- A Model for MOS Effective Channel Mobility with Emphasis in the Subthreshold and Transition RegionKewei Yang, Richard C. Meitzler, Andreas G. Andreou. 431-434
- Transfer Function Design for Delta-Sigma ConvertersS. Jantzi, C. Ouslis, Adel S. Sedra. 433-436
- Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI CircuitsHarish Kriplani, Farid N. Najm, Ibrahim N. Hajj. 435-438
- Faster, Higher-Quality Training of Feedforward Neural Network ModelsJohn R. Deller Jr., S. D. Hunt. 435-438
- Analysis of Tones in the Double Loop SigmaDelta Modulator with Unstable Filter DynamicsMariam Motamed, Seth Sanders, Avideh Zakhor. 437-440
- A Timing Model for VLSI CMOS Circuits Verification and OptimizationLuís Felipe Uebel, Sergio Bampi. 439-442
- An Appraoch of Sequential-Like Parallel Algorithm in Boltzmann MachineHongbing Zhu, Mamoru Sasaki, Fumio Ueno, Takahiro Inoue. 439-442
- Fault-Tolerant Linear Convolution using Residue Number SystemsM. G. Parker, Mohammed Benaissa. 441-444
- Higher-Order Delta-Sigma Frequency to Digital ConversionIan Galton. 441-444
- Hierarchical Statistical Verification of Large Full Custom CMOS CircuitsA. B. van der Wal, Robert G. J. Arendsen, Aarnout Brombacher, O. E. Herrmann. 443-446
- Modeling OpAmp-Induced Harmonic Distorition for Switched-Capacitor Sigma-Delta Modulator DesignF. Medeiro, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez, José L. Huertas. 445-448
- A Systematic Search Method for Obtaining Multiple Local Optimal Solutions of Nonlinear Programming ProblemsHsiao-Dong Chiang, Chia-Chi Chu. 447-450
- Sensitivity Analysis for Minimization of Input Data Dimension for Feedforward Neural NetworkJacek M. Zurada, Aleksander Malinowski, Ian Cloete. 447-450
- Tone Supression in General Double-Loop Sigma-Delta Modulators using ChaosSøren Hein. 449-452
- Extending Winograd s Small Convolution Algorithm to Longer LengthsIvan W. Selesnick, C. Sidney Burrus. 449-452
- Pleasures, Perils and Pitfalls of Symbolic AnalysisFrancisco V. Fernández, Georges G. E. Gielen, Lawrence Huelsman, Agnieszka Konczykowska, Stefano Manetti, Willy M. C. Sansen, Jiri Vlach. 451-457
- Wide-Range Variable Dynamics Using Switched-Capacitor NeuromorphsJohn G. Elias, David P. M. Northmore, Samer M. Meshreki. 451-454
- A Complex Bandpass Delta-Sigma Converter for Digital RadioS. Jantzi, Kenneth W. Martin, W. Martin Snelgrove, Adel S. Sedra. 453-456
- Man: Mass Attraction NetworkMahmut Hilmi Erdem, Yusuf Ozturk. 455-458
- Muliplierless Realization Structure of Adaptive Filters by Nonuniform Quantization of Input SignalDongning Li, Yong Ching Lim. 457-459
- Analysis and Design of Adaptive Self-Trimming Technique for A/D ConvertersZhiqiang Gu, W. Martin Snelgrove. 457-460
- Signal Integrity Analysis and Optimization of VLSI Interconnects using Neural Network ModelsQi-Jun Zhang, Michel S. Nakhla. 459-462
- Sensitivity to Errors in Artificial Neural Networks: a Behavioural ApproachCesare Alippi, Vincenzo Piuri, Mariagiovanna Sami. 459-462
- Limit Cycles and Asymptotic Stability of Delta-Operator Formulated Discrete-Time Systems in Fixed-Point ArithmeticKamal Premaratne, Peter H. Bauer. 461-464
- A Mismatch Independent DNL Pipelined Analog to Digital ConverterJohn Wu, Bosco Leung, Sehat Sutarja. 461-464
- Dynamically-Wiresized Elmore-Based Routing ConstructionsTodd D. Hodes, Bernard A. McCoy, Gabriel Robins. 463-466
- A 6-Bit 50MHz Current-Subtracting Two Step Flash ConverterAndrew Cable, Ramesh Harjani. 465-468
- Solution of the Missing Cure Problem by Artificial Neural NetworkKai-Kou R. Yu, Sze-Fong Yau. 467-470
- A Hierarchical Approach to Clock Routing in High Performance SystemsWasim Khan, Sreekrishna Madhwapathy, Naveed A. Sherwani. 467-470
- Recovery of Multiband Signals Using Finite SamplesXiang-Gen Xia, C. C. Jay Kuo, Zhen Zhang. 469-472
- A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero PulsesSeung-Jai Min, Eel-Wan Lee, Soo-Ik Chae. 471-474
- Over-the-Cell Routing with Cell Orientations ConsiderationT. W. Her, D. F. Wong. 471-474
- Neural Networks Using Bit Stream Arithmetic: a Space Efficient ImplementationValentina Salapura. 475-478
- A High Performance General Purpose Multi-Point Signal RouterNaresh Kumar Seghal, C. Y. Roger Chen, John M. Acken. 475-478
- Design of Limit-Cycle-Free Recursive Transfer Functions for Fixed-Point Direct Form ImplementationTimo I. Laakso, Markus Lang, Tapio Saramäki. 477-480
- A Switched-Current Bandpass Delta-Sigma ModulatorSrinivas V. Pattamatta, Praveen Manapragada, Vineet Dalal, Richard Schreier. 477-480
- A High-Speed Integrated Hamming Neural ClassifierDavid Grant, John Taylor, Paul Houselander. 479-482
- Analysis and Experiments for a Parallel Solution to the All Pairs Shortest Path ProblemIra Pramanick, Hyder Ali. 479-482
- The Application of Redundant Number Systems to Digital Sigma-Delta ModulatorsDavid M. Hosack, John I. Sewell. 481-484
- A Gaussian Synapse Circuit for Analog VLSI Neural NetworksJoongho Choi, Bing J. Sheu, Josephine C.-F. Chang. 483-486
- Synthesis of Fixed Point Low Roundoff Noise Digital Filters with no Limit CycleM. F. Fahmy, G. A. Raheem. 485-488
- A Fully Differential Switched-Current Delta-Sigma Modulator Using a Single 3.3-V Power Supply VoltageNianxiong Tan, Sven Eriksson. 485-488
- CMOS Implementation of Associative Memory Using Cellular Neural Network Having Adjustable Template CoefficientsAri Paasio, Kari Halonen, Veikko Porra. 487-490
- PHIroute: A Parallel Hierarchical Sea-of-Gates RouterHenning Spruth, Frank M. Johannes, Kurt Antreich. 487-490
- Optimal (Bandpass) Continuous-Time Sigma-Delta ModulatorOmid Shoaei, W. Martin Snelgrove. 489-492
- Floating-point Quasi-Maximum Accuracy Arithmetics for Digital Signal ProcessingAdam Dabrowski, Marek Olejniczak. 489-492
- Setting and Validating Precision Requirements in the Digital VLSI Implementation of a Neural Defect-Identifier for Machined ObjectsCesare Alippi, Luciano Briozzo. 491-494
- An Algorithm for the Place-and-Route Problem in the Layout of Analog CircuitsJuan A. Prieto, José M. Quintana, Adoración Rueda, José L. Huertas. 491-494
- A 3.3 Volt Electronically Tunable Active Filter Usable to Beyond 1 GHzDouglas Frey. 493-496
- High-Performance IIR QMF Banks for Speech Subband CodingZhongnong Jiang, Abeer A. Alwan, Alan N. Willson Jr.. 493-496
- An Analogue CMOS Defuzzication Circuit with Representation of Triangular Membership FunctionsS. Pammu, Steven F. Quigley. 495-498
- Polarity-Coincidence Filter Banks and Nondestructive EvaluationTruong Q. Nguyen, Sriram Jayasimha. 497-500
- A 1.75V Rail-to-Rail CMOS Op AmpAbdulkerim L. Coban, Phillip E. Allen. 497-500
- Quadrature Modulated Filter BanksS. C. Chan. 501-504
- Lov-Voltage (3.3V) / Low-Power (100muW), 2MHZ CMOS Comparator for 12-BIT ADCSPhilippe Deval, Vlado Valencic, Francis Anghinolfi. 501-504
- Analog CMOS Implementation of Neural Network for Adaptive Signal ProcessingHwa-Joon Oh, Fathi M. A. Salam. 503-506
- On McClellan Transform and 2-D QMF BanksK. Kurosawa. 505-508
- Low-Voltage Low-Power Fully-Integratable Automatic Gain ControlsWouter A. Serdijn, Albert C. van der Woerd, Jan Davidse, Arthur H. M. van Roermund. 505-508
- Analysis and Optimum Design of the FFBYong Ching Lim, Behrouz Farhang-Boroujeny. 509-512
- A Two-Stage Decimation Filter Design Technique for Oversampling Delta-Sigma A/D ConvertersNianxiong Tan, Sven Eriksson. 513-516
- The Design of CMOS Transconductor for High Frequency Continuous-Time Filter ApplicationsF. Yang, P. Loumeaeu, Kamran Azadet, P. Senn. 513-516
- 1-GHz Operational Amplifier with Multipath Nested Miller CompensationKlaas-Jan de Langen, Johan H. Huijsing. 517-520
- A Multiple Exchange Remez Algorithm for Complex FIR Filter Design in the Chebyshev SenseLina J. Karam, James H. McClellan. 517-520
- A High Dynamic Range 100Mhz AGC-Amplifier with a Linear and Temperature Compensated Gain ControlH. Riihihuhta, Kari Halonen, Kari Koli. 521-524
- A BiCMOs Current-Feedback Operational Amplifier with a 60 dB Constant Bandwidth RangeKimmo Koli, Kari Halonen. 525-528
- A Linear Phase Maximally Flat Low-Pass FIR FilterMagdy T. Hanna. 525-528
- Implementation of the IPFE Algorithm for Synthesis of High Order Recursive FiltersM. Price, Mark B. Sandler. 529-532
- Low Voltage Current Mirrors for Built-in Current SensorsJaime Ramírez-Angulo. 529-532
- A Design Technique for Polyphase Decimators with Binary Constrained Coefficients for High Resolution A/D ConvertersArtur Krukowski, Izzet Kale, Richard C. S. Morling, K. Hejn. 533-536
- Linear Phase IIR Filters Composed of Two Parallel Allpass SectionsBartlomiej Jaworski, Tapio Saramäki. 537-540
- Array Based Fuzzy Inference Mechanism Implemented with Current-Mode CMOS CircuitsBin-Da Liu, Chun-Yueh Huang. 537-540
- Analysis of IC Op-Amp Power-Supply Current SensingW. J. Su, F. J. Lidgey, S. Porta, Q. S. Zhu. 541-544
- Wide Range Gain Programmable Class AB Current Mirrors for Low Supply OperationJaime Ramírez-Angulo. 545-548
- Generalizations of Classical Recursive Digital Filters and Their Design with the Aid of a Remez-Tupe AlgorithmTapio Saramäki. 549-552
- The Design of the CMOS Current-Mode General-Purpose Analog ProcessorLiang-Hung Lu, Chung-Yu Wu. 549-552
- Low-Dimensional Conditions for Global Asymptotic Stability of M-D Nonlinear Digital FiltersPeter H. Bauer. 553-556
- A Modular Current-Mode High-Precision Winner-Take-All CircuitTeresa Serrano-Gotarredona, Bernabé Linares-Barranco. 557-560
- A New Algorithm and its VLSI Architecture Design for Connected Component LabellingShuenn-Der Jean, Chi-Min Liu, Chih-Chi Chang, Zen Chen. 565-568
- Efficient Noise Analysis Methods for Large Non-ideal SC and SI CircuitsZ. Q. Shang, John I. Sewell. 565-568
- A Multi-Input Multi-Output Recursive Least Squares Algorithm with Applications to LORAN-C TransmitterMurali Tummala, John D. Wood. 569-572
- Switched-Current Filters Using Component SimulationJones Schechtman, Antônio Carlos M. de Queiroz, Luiz Pereira Calôba. 569-572
- An Efficient Least-Squares Approach for the Design of Two-Dimensional Linear-Phase Nonrecursive FiltersS. Sunder, Ravi P. Ramachandran. 577-580
- On Signal-Flow Graph Analysis of Multiphase SC NetworksTomás Dostal. 585-588
- A New 2-D Zero Phase Digital Filter Design with Quadrantally Symmetric or Antisymmetric PropertiesJ. Y. Chang, W. H. Wang. 585-588
- Audio Sigma-Delta-Modulator Implementaion using Class AB Compact Switched Current Memory CellsHåkan Träff, Sven Eriksson. 589-592
- Two-Dimensional Spectral Representation with ApplicationsHaoping Yu, Wasfy B. Mikhael. 589-592
- Synthesis of Switched-Capacitor Inductance Simulation CircuitsTomás Dostál. 593-594
- Optimal Minimax Two-Dimensional FIR Design Using a Multiple Simplex ExchangeDaniel Burnside, Thomas W. Parks. 593-596
- Switched Capacitor Dual-Collector MagnetotransistorsPiero Malcovati, R. Castagnetti, Henry Baltes, Carlos Azeredo Leme, Franco Maloberti. 595-598
- Current-Mode Network TransformationsMehul Desai, Peter B. Aronhime, Jacek M. Zurada. 599-602
- A Double-MOSFET Switched-Capacitor Auto-Tuned High Frequency FilterMing-Chang Hong, Wen-Chi Wu, Chrong-Kuang Wang. 603-606
- Part 1 - Electronics in Transition, The Tools and Technologies for 2000 ADBarrie Gilbert. 611-634
- Two-Dimensional Optimal Algorithms for Image Compression using ARMA predictorsShomit M. Ghosh, Wasfy B. Mikhael. 613-616
- IFS Image Coding Using an Orthonormal BasisMonson H. Hayes, Greg Vines. 621-624
- AR Spectrum Estimation Based on Wavelet RepresentationFernando Gil Resende, Keiichi Tokuda, Mineo Kaneko. 625-628
- An Efficient Design Method for Optimal Weighted Median FilteringRuikang Yang, Moncef Gabbouj, Yrjö Neuvo. 633-636
- Part 2 - 101 Ways to Make a Circuit FailChris Toumazou, James Bryant, Phillip E. Allen, Derek F. Bowers, Barrie Gilbert, Aarnout Brombacher. 635-640
- A Programmable 1.8-18MHz High-Q Fully-Differential Continuous-Time Filter with 1.5-2 Power SupplyJoseph T. Nabicht, Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo. 653-656
- The Opto-Electronic Transconductor and Its ApplicationsTongtod Vanisri, Chris Toumazou. 657-660
- Integrated BiCMOS IF-Modules for Mobile Telecommunication ApplicationsKari Halonen, Veikko Porra, P. Alinikula, K. Koli, H. Riihihuhta, J. Hännikäinen. 661-664
- Design of High-Frequency BiCMOS Continuous-Time Filters with Low-Output Impedance TransconductorA. Baschirotto, F. Rezzi, R. Alini, R. Castello. 665-668
- Two Approaches for Current-Mode Filters using Voltage Follower and Transconductance Multipliers Building BlocksJaime Ramírez-Angulo, Edgar Sánchez-Sinencio. 669-672
- Time Interval Digitization with an Integrated 32-Phase OscillatorElvi Räisänen-Ruotsalainen, Timo Rahkonen, Juha Kostamovaara. 673-676
- Mocromodelling Opterational AmplifiersJan H. A. Feijes, Ron Hogervorst, Johan H. Huijsing. 681-684
- The Design of Oscillators using the Cascode CircuitWing Shing Chan, Kim Fung Tsang, G. B. Morgan. 689-692
- Optimized Design of 4 Stage Dickson Voltage MultiplierGiuseppe Di Cataldo, Gaetano Palumbo. 693-696
- Bifurcation and Chaos in CMOS Inverters Ring OscillatorCong-Kha Pham, Mamoru Tanaka, Katsufusa Shono. 697-700
- MOS Active Attenuators for Analog ICs and their Applications to FInite Gain AmplifiersJoon-Yub Kim, Randall L. Geiger. 701-704
- ASP 12: Forum - Analog Electronics - a European Speciality?Rudy J. van de Plassche, Bob Adams, Gerson A. S. Machado, Gabor C. Temes, Hugo De Man. 705-710
- A Comparison Study of SC Biquads in the Realisation of SC FiltersLu Yue, John I. Sewell. 711-714
- A Parallel Trimming Method of Offset Reduction for Comparators and AmplifiersMing Zhang, Francis Devos, Jean-François Pône, Yang Ni. 715-718
- Gain Enhancement Technique for High-Speed Switched-Capacitor CircuitsS. Brigati, Franco Maloberti, Guido Torelli. 719-722
- SC FIR Interpolation Filters using Parallel Cyclic NetworksKyoko Kato, Toshiharu Kikui, Yoshinori Hirata, Toyoji Matsumoto, Tsuyoshi Takebe. 723-726
- A Programmable Switched-Capacitor FilterJosé Silva-Martínez. 727-730
- High-Speed CMOS Current ComparatorsJoão Pedro A. Carreira, José E. Franca. 731-734
- Q-Enhancing Technique for High Speed Active InductorsRisto Kaunisto, Petteri Alinikula, Kari Stadius. 735-738
- A High-Accuracy High-Speed CMOS Current ComparatorGiovanni Palmisano, Gaetano Palumbo, Salvatore Pennisi. 739-742
- High Slew Rate, Low Voltage BiCMOS and Bipolar Operational Amplifier Architectures with Rail to Rrail Common Mode Input Voltage SwingJaime Ramírez-Angulo. 743-746
- Charge Pump for optimal dynamic range filtersG. L. E. Monna, J. C. Sandee, Chris J. M. Verhoeven, G. Groenewold, Arthur H. M. van Roermund. 747-750
- New Single-Capacitor MOSFET-C Integrators: Analysis, Design & ApplicationsR. Brannen, Shigetaka Takagi, Mohammed Ismail, Nobuo Fujii. 751-754
- New Dual-Input Voltage Controlled Integrator/Differentiator and their Digital ControlDebajyoti Pal, S. K. Sanyal, R. Nandi. 755-758
- Fully Balanced Second Order Active Filter Circuits Having Few Op-ampsDavid H. Horrocks. 759-762
- A Method for Dynamic Range Maximization for a Class of Integrated Active-RC FiltersN. G. Maratos, G. T. Ioannidis. 763-766
- Computation of Filters Derived from Lowpass Prototypes through Rational TransformationsJean Le Bihan, François Ropars. 767-770
- The Continuous-Time VHF Lowpass Filter Design Using Finite-Gain Current and Voltage Amplifiers and Special Q-Enhancement CircuitChung-Yu Wu, Heng-Shou Hsu. 771-774
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- On the search for a universal active elementAlfonso Carlosena, Rafael Cabeza, Luis Serrano. 779-782
- Low Output Conductance Composite Mosfets for high Frequency Analog DesignCarlos Galup-Montoro, Márcio C. Schneider, I. J. B. Loss. 783-786
- Analogue Active Filters with Two-Tone Large-Signal ExcitationP. Bowron, A. A. Muhieddine. 787-790
- Recursive Allpass Filter Design using Least-Squares TechniquesS. Sunder, V. Ramachandran. 791-794