Brian S. Cherkauer - researchr alias

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Viewing Publication 1 - 10 from 10

2009

A 65 nm 2-Billion Transistor Quad-Core Itanium ProcessorBlaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer. jssc, 44(1):18-31, 2009. [doi]

2008

A 65nm 2-Billion-Transistor Quad-Core Itanium® ProcessorBlaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles. isscc 2008: 92-93 [doi]

2007

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 CacheStefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora. jssc, 42(1):17-25, 2007. [doi]

2004

Itanium 2 Processor 6M: Higher Frequency and Larger L3 CacheStefan Rusu, Harry Muljono, Brian S. Cherkauer. micro, 24(2):10-18, 2004. [doi]

2003

A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cacheStefan Rusu, Jason Stinson, Simon Tam 0001, Justin Leung, Harry Muljono, Brian S. Cherkauer. jssc, 38(11):1887-1895, 2003. [doi]

1995

Design of tapered buffers with local interconnect capacitanceBrian S. Cherkauer, Eby G. Friedman. jssc, 30(2):151-155, February 1995. [doi]

A unified design methodology for CMOS tapered buffersBrian S. Cherkauer, Eby G. Friedman. tvlsi, 3(1):99-111, 1995. [doi]

1994

Channel width tapering of serially connected MOSFET s with emphasis on power dissipationBrian S. Cherkauer, Eby G. Friedman. tvlsi, 2(1):100-114, 1994. [doi]

Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer DesignBrian S. Cherkauer, Eby G. Friedman. iscas 1994: 111-114

1993

The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETsBrian S. Cherkauer, Eby G. Friedman. iscas 1993: 2110-2113

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