Beomsup Kim - researchr alias

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Viewing Publication 1 - 41 from 41

2017

A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOSYashar Rajavi, Mohammad Mahdi Ghahramani, Alireza Khalili, Amirpouya Kavousian, Beomsup Kim, Michael P. Flynn. jssc, 52(10):2735-2745, 2017. [doi]

2012

Low-Voltage Low-Power 1.6 GHz Quadrature Signal Generation Through Stacking a Transformer-Based VCO and a Divide-by-TwoShen Wang, Vipul Chawla, Dong Sam Ha, Beomsup Kim. tcas, 59-I(12):2901-2910, 2012. [doi]

2011

A combined VCO and divide-by-two for low-voltage low-power 1.6 GHz quadrature signal generationShen Wang, Dong Sam Ha, Beomsup Kim, Vipul Chawla. cicc 2011: 1-4 [doi]

2005

A DLL-Based Frequency Synthesizer with Selective Reuse of a Delay Cell Scheme for 2.4 GHz ISM BandSeok Kang, Beomsup Kim. ieicet, 88-C(1):149-153, 2005. [doi]

A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizerJinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, C. S. G. Conroy, Beomsup Kim. jssc, 40(2):462-471, 2005. [doi]

An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA ApplicationsJaesang Lim, Yongchul Song, Jeong Pyo Kim, Beomsup Kim. ieicet, 88-A(12):3677-3680, 2005. [doi]

Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring OscillatorsJaesang Lim, Jaejoon Kim, Beomsup Kim. ieicet, 88-A(4):1084-1089, 2005. [doi]

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integratorsJae Hoon Shim, In-Cheol Park, Beomsup Kim. jssc, 40(4):918-925, 2005. [doi]

Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators"Jae Hoon Shim, In-Cheol Park, Beomsup Kim. jssc, 40(11):2339, 2005. [doi]

Hybrid ΣΔ modulators with adaptive calibrationJae Hoon Shim, In-Cheol Park, Beomsup Kim. tcas, 52-I(5):885-893, 2005. [doi]

2004

A quadrature digital synthesizer/mixer architecture using fine/coarse coordinate rotation to achieve 14-b input, 15-b output, and 100-dBc SFDRYongchul Song, Beomsup Kim. jssc, 39(11):1853-1861, 2004. [doi]

Quadrature direct digital frequency synthesizers using interpolation-based angle rotationYongchul Song, Beomsup Kim. tvlsi, 12(7):701-710, 2004. [doi]

A 14-b direct digital frequency synthesizer with sigma-delta noise shapingYongchul Song, Beomsup Kim. jssc, 39(5):847-851, 2004. [doi]

2003

2001

2000

1999

16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular TelephonyTae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young-gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim. aspdac 1999: 49 [doi]

A low-noise, 900-MHz VCO in 0.6-μm CMOSChan Hong Park, Beomsup Kim. jssc, 34(5):586-591, 1999. [doi]

1998

1997

1995

Adaptive Carrier Recovery Using Multi-Order DPLL for Mobile Communication ApplicationsByungjin Chun, Beomsup Kim, Yong Hong Lee. iscas 1995: 1082-1085

A digital audio signal processor for cellular phone applicationJeongsik Yang, Chanhong Park, Beomsup Kim. aspdac 1995: [doi]

1994

PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer DesignBeomsup Kim, Todd C. Weigandt, Paul R. Gray. iscas 1994: 31-34

Analysis of Timing Jitter in CMOS Ring OscillatorsTodd C. Weigandt, Beomsup Kim, Paul R. Gray. iscas 1994: 27-30

1993

Optical MMSE gear-shifting algorithm for the fast synchronization of DPLLBeomsup Kim. iscas 1993: 172-175

1991

A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOSYuh-Min Lin, Beomsup Kim, Paul R. Gray. jssc, 26(4):628-636, April 1991. [doi]

1990

A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOSBeomsup Kim, David N. Helman, Paul R. Gray. jssc, 25(6):1385-1394, December 1990. [doi]

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2012

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1991

1990

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