Jae Hoon Shim - researchr alias

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Viewing Publication 1 - 18 from 18

2024

Enhancing Semiconductor X-RAY Images: A Framework Combining Denoising and Super-Resolution Modules With a Novel DatasetJae Hoon Shim, Min Woo Kim, Tae Gyu Lim, Byungseok Min, Sang Hwa Lee, Nam Ik Cho. apsipa 2025: 1-6 [doi]

2023

An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop DetectorJaejin Kim, Gunmo Koo, Seongmin Lee, Jae Hoon Shim, Kunhee Cho. tcasI, 70(12):4975-4985, December 2023. [doi]

An Output-Capacitor-Free Adaptive-Frequency Digital LDO with a 420-mA Load Current and a Fast Settling TimeDong-Jick Min, Jun-Gi Lee, Kunhee Cho, Jae Hoon Shim. iscas 2023: 1-5 [doi]

2021

2018

A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing DetectorDong-Jick Min, Sun Youl Choi, Jae Hoon Shim. icecsys 2018: 817-820 [doi]

Modified adaptive support weight and disparity search range estimation schemes for stereo matching processorsSeung Ho Ok, Jae Hoon Shim, Byungin Moon. tjs, 74(12):6665-6690, 2018. [doi]

3D die-stacked DRAM thermal management via task allocation and core pipeline controlChangho Yoon, Jae Hoon Shim, Byungin Moon, Joonho Kong. ieiceee, 15(3):20171253, 2018. [doi]

2017

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching ProcessorsSeung Ho Ok, Yong-Hwan Lee, Jae Hoon Shim, Sung Kyu Lim, Byungin Moon. sensors, 17(2):426, 2017. [doi]

2010

Charge Pump circuit with wide range digital leakage current mismatch compensatorSangjin Byun, Jae Hoon Shim. ieiceee, 7(23):1709-1713, 2010. [doi]

2006

A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase DetectorSangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu. isscc 2006: 1324-1333 [doi]

A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase DetectorSangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu. jssc, 41(11):2566-2576, 2006. [doi]

2005

A third-order /spl Sigma//spl Delta/ modulator in 0.18-/spl mu/m CMOS with calibrated mixed-mode integratorsJae Hoon Shim, In-Cheol Park, Beomsup Kim. jssc, 40(4):918-925, 2005. [doi]

Correction to "A Third-Order$Sigma Delta $Modulator in 0.18-$muhboxm$CMOS With Calibrated Mixed-Mode Integrators"Jae Hoon Shim, In-Cheol Park, Beomsup Kim. jssc, 40(11):2339, 2005. [doi]

Hybrid ΣΔ modulators with adaptive calibrationJae Hoon Shim, In-Cheol Park, Beomsup Kim. tcas, 52-I(5):885-893, 2005. [doi]

2003

A hybrid delta-sigma modulator with adaptive calibrationJae Hoon Shim, In-Cheol Park, Beomsup Kim. iscas 2003: 1025-1028 [doi]

2001

A 500-Mb/s quadruple data rate SDRAM interface using a skew cancellation techniqueSung-Ho Wang, Jeongpyo Kim, Joonsuk Lee, Hyoung Sik Nam, Young-gon Kim, Jae Hoon Shim, Hyung Ki Ahn, Seok Kang, Bong Hwa Jeong, Jin-Hong Ahn, Beomsup Kim. jssc, 36(4):648-657, 2001. [doi]

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