Abstract is missing.
- 3D-Stacked CMOS SPAD Image Sensors: Technology and ApplicationsEdoardo Charbon, Claudio Bruschini, Myung-Jae Lee. 1-4 [doi]
- A novel sub-10 ps resolution TDC for CMOS SPAD arrayVincenzo Sesta, Federica A. Villa, Enrico Conca, Alberto Tosi. 5-8 [doi]
- Transient Response of a 0.35µm CMOS SPAD with Thick Absorption ZoneBernhard Goll, Michael Hofbauer, Bernhard Steindl, Horst Zimmermann. 9-12 [doi]
- A Triple Integration Timing Scheme for SPAD Time of Flight Imaging Sensors in 130 nm CMOSDaniel Morrison, Simon Kennedy, Dennis Delic, Mehmet R. Yuce, Jean-Michel Redoute. 13-16 [doi]
- 2×192 Pixel CMOS SPAD-Based Flash LiDAR Sensor with Adjustable Background RejectionMaik Beer, Charles Thattil, Jan F. Haase, Werner Brockherde, Rainer Kokozinski. 17-20 [doi]
- 2 Area w/ 2D Digital-Pre-Distortion and Package CombinerAntonio Passamani, Davide Ponton, Andreas Wolter, Gerhard Knoblinger, Andrea Bevilacqua. 21-24 [doi]
- Compact Transformerless K-Band PA with more than 33% PAE and 14.8 dBm Output Power in 65 nm Bulk CMOSSoenke Vehring, Georg Böck. 25-28 [doi]
- Design of 65-nm CMOS Transformer-Based Impedance Matching for LTE Power Amplifier ApplicationsGiap Luong, Eric Kerherve, Jean-Marie Pham, Pierre Medrel. 29-32 [doi]
- Augmentation of Class-E PA Reliability under Load Mismatch ConditionsJeroen Ponte, Ali Ghahremani, Maikel Huiskamp, Anne-Johan Annema, Bram Nauta. 33-36 [doi]
- A 17.3-20.2 GHz Fully Integrated Linear Balanced Power Amplifier in 130nm BiCMOS TechnologyPotereau Manuel, Deltimple Nathalie, Ghiotto Anthony, Dematos Magali. 37-40 [doi]
- A 1-60 GHz 9.6 mW 0.18 V Output-Swing Static Clock Divider Circuit in 45-nm SOI CMOSSami Ur Rehman, Ali Ferchichi, Mohammad Mahdi Khafaji, Corrado Carta, Frank Ellinger. 41-44 [doi]
- A Novel Half-Rate Dual-Response Phase Detector Implementation for a 25-28.3 Gb/s Clock and Data Recovery CircuitBortecene Terlemez, Burak Dundar. 45-48 [doi]
- A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS ConversionRyosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine. 49-52 [doi]
- Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over EthernetSimon Buhr, Martin Kreissig, Frank Ellinger. 53-56 [doi]
- A Framework for Automatic Generation of Fully Synthesizable ADPLLShinya Ubukata, Satoshi Komatsu. 57-60 [doi]
- Experimental 5G New Radio integration with VLCLina Shi, Wei Li, Xun Zhang, Yue Zhang, Gaojie Chen, Andrei Vladimirescu. 61-64 [doi]
- LoRa Physical Layer Principle and Performance AnalysisGuillaume Ferré, Audrey Giremus. 65-68 [doi]
- A Novel Physical Layer Encryption Scheme to Counter Eavesdroppers in Wireless CommunicationsPrasidh Ramabadran, David Malone, Sidath Madhuwantha, Pavel Afanasyev, Ronan Farrell, John Dooley, Bill O'Brien. 69-72 [doi]
- Hardware design of Euclidean Projection modules for ADMM LDPC decodingHayfa Ben Thameur, Bertrand Le Gal, Nadia Khouja, Fethi Tlili, Christophe Jégo. 73-76 [doi]
- Interference Cancellation Architecture for Pipelined Parallel MIMO DetectorsByeong Yong Kong, Jaehwan Jung, In-Cheol Park. 77-80 [doi]
- EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGAKathirgamaraja Pradeep, Kamalakkannan Kamalavasan, Ratnasegar Nathecsan, Ajith Pasqual. 81-84 [doi]
- Constant Matrix Multiplication with Ternary AddersMartin Hardieck, Martin Kumm, Patrick Sittel, Peter Zipf. 85-88 [doi]
- From multicore LDPC decoder implementations to FPGA decoder architectures: a case studyYann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo. 89-92 [doi]
- Permutation-Only FPGA Realization of Real-Time Speech EncryptionMohamed F. Tolba, Wafaa S. Sayed, Ahmed G. Radwan, Salwa K. Abd-El-Hafiz, Ahmed M. Soliman. 93-96 [doi]
- Parity Based In-Place FFT Architecture for Continuous Flow ApplicationsVasileios Kitsakis, E. A. Papatheofanous, Dionisios I. Reisis, George Lentaris, Dimitrios Soudris. 97-100 [doi]
- Why and How VCO-based ADCs can improve instrumentation applicationsEric Gutierrez, Pieter Rombouts, Luis Hernández. 101-104 [doi]
- All-Digital-Very-Scalable-ADC TAD Showing Scaling-Effect in 40/16nm-CMOS TechnologyTakamoto Watanabe. 105-108 [doi]
- Ring Counters as Phase Accumulator in VCO-Based ADCsMark Vesterbacka, Vishnu Unnikrishnan. 109-112 [doi]
- Ring Oscillator Based Delta-Sigma ADCsMohammadhadi Danesh, Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal. 113-116 [doi]
- Improving the robustness and drift resilience of CMOS BBPLL-based time-based sensor interfacesGeorges G. E. Gielen, Jorge Marin, Elisa Sacco. 117-120 [doi]
- A CMOS Squarer Based Nonlinear Filter for Spike DetectionJulio Saldaña Pumarica, Emilio Del Moral Hernandez. 121-124 [doi]
- An Integrated Sensor IBC Implant TransceiverAssefa Kassa Teshome, Behailu Kibret, Daniel T. H. Lai. 125-128 [doi]
- A Low Power Packet Detection Algorithm for FM-UWB PHY for IEEE 802.15.6 WBANAtef H. Bondok, Ahmed Shalaby, Mohammed S. Sayed. 133-136 [doi]
- An Experimentally-Validated Verilog-A SPAD Model Extracted from TCAD SimulationJuan Manuel Lopez-Martinez, Ion Vornicu, Ricardo Carmona-Galán, Ángel Rodríguez-Vázquez. 137-140 [doi]
- A new quantum random generator based on a single photon position sensitive deviceNicola Massari, Hesong Xu. 141-144 [doi]
- Analytical Compact Model for PMUTs InterfacesMohammed Bedier, Gwenael Bechet, Franck Badets. 145-148 [doi]
- Fully Integrated CMOS-PMUT TransceiverI. Zamora, E. Ledesma, Arantxa Uranga, Núria Barniol. 149-152 [doi]
- Occupancy Oscillations and Electron Transfer in Multiple-Quantum-Dot Qubits and their Circuit RepresentationPanagiotis Giounanlis, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski. 153-156 [doi]
- Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challengesPascal Vivet, Sebastien Thuries, Olivier Billoint, Sylvain Choisnet, Didier Lattard, Edith Beigné, Perrine Batude. 157-160 [doi]
- 28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep LearningHaruki Mori, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto. 161-164 [doi]
- Low-Power Resistive Associative Processor Implementation Through the Multi-CompareHasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi. 165-168 [doi]
- CubeSats for Future Science and Internet of Space: Challenges and OpportunitiesAnna Gregorio, Federico Alimenti. 169-172 [doi]
- A Fully-Integrated 60-GHz Voltage-Controlled Oscillator Synchronized by Optoelectronic SignalUroschanit Yodprasit, Marcel Kroh, Stefan Simon, Thomas Mausolf, Wolfgang Winkler. 173-176 [doi]
- A 1-9 GHz wideband downconverter with noise cancellation and Gm-boosted transconductance cellHugo Vallee, Thierry Taris, Thierry Mesnard, Gilles Montoriol, Xavier Hours. 177-180 [doi]
- Experimental Demonstration of a 65 nm Integrated CMOS Waveform Generator for 5G sub-6GHz StandardPierre Bisiaux, Francois Rivet, Yoan Veyrac, Yann Deval. 181-184 [doi]
- Human Body Communication Channel Characterization for Leadless Cardiac PacemakersMirko Maldari, Karima Amara, Ismael Rattalino, Chadi Jabbour, Patricia Desgreys. 185-188 [doi]
- Internet of Wine: A Low-cost Solution for Stock Management ImprovementAcchiardi Mathieu, Kern Jonathan, Guillaume Ferré. 189-192 [doi]
- HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC DesignAlessandro Via Piana Saggiorato, Fábio Luís Livi Ramos, Bruno Zatt, Marcelo Schiavon Porto, Sergio Bampi. 193-196 [doi]
- On HEVC Robustness to Integer Motion Estimation PruningLuiz Henrique Cancellier, Ismael Seidel, José Luís Güntzel. 197-200 [doi]
- Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p VideosGustavo Sanchez, Ramon Fernandes, Rodrigo Cataldo, Luciano Agostini, César A. M. Marcon. 201-204 [doi]
- Least-Squares Approximation Surfaces for High Quality Intra-Frame Prediction in Future Video StandardsRamon Fernandes, Gustavo Sanchez, Rodrigo Cataldo, Luciano Agostini, César A. M. Marcon. 205-208 [doi]
- Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT DevicesShuto Kanzaki, Tetsuya Hirose, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa. 209-212 [doi]
- An Integrated Low Drop Out Regulator with Independent Self Biasing Start Up CircuitLeo Rolff, Eva Schulte Bocholt, Ralf Wunderlich, Stefan Heinen. 213-216 [doi]
- Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-SimulationAbhishek Koneru, Aida Todri-Sanial, Krishnendu Chakrabarty. 217-220 [doi]
- Single Inductor Multiple Output Buck Converter with Auxiliary Current Source Based ControlSeungchul Jung, Sang Joon Kim. 221-224 [doi]
- A Tracking Quantizer for Continuous Time Quadrature Bandpass Sigma-Delta ModulatorsTobias Saalfeld, Markus Scholl, Christoph Beyerstedt, Ralf Wunderlich, Stefan Heinen. 225-228 [doi]
- StrongARM Latch Comparator Performance Enhancement by Implementing Clocked Forward Body BiasingAbdullah Alshehri, Mohammed Al-Qadasi, Abdullah S. Almansouri, Talal Al-Attar, Hossein Fariborzi. 229-232 [doi]
- A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold LoweringGiuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo. 233-236 [doi]
- Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME InterpolatorWagner Penny, Mariana Ucker, Italo Machado, Luciano Agostini, Daniel Palomino, Marcelo Schiavon Porto, Bruno Zatt. 237-240 [doi]
- A Fully Programmable eFPGA-Augmented SoC for Smart-Power ApplicationsF. Renzini, D. Rossi, Eleonora Franchi Scarselli, Claudio Mucci, Roberto Canegallo. 241-244 [doi]
- DROP: Distributed Run-Time and Power Constraint Mapping for Many-Core SystemsMohammad Mohammad, Iraklis Anagnostopoulos. 245-248 [doi]
- Low Power and High Speed Static CMOS Digital Magnitude ComparatorsCostas Efstathiou, K. Dimolikas, C. Papaioannou, Y. Tsiatouhas. 249-252 [doi]
- Design of a Generalized Fractional-Order PID Controller Using Operational AmplifiersEmmanuel A. Gonzalez, Vassilis Alimisis, Costas Psychalinos, Aleksei Tepljakov. 253-256 [doi]
- A Rectifier Circuit Using Add-Differentiate IC with a Minimal Number of CMOS TransistorsIzzet Cem Göknar, Elham Minayi. 257-260 [doi]
- Design of a Low-Voltage EEG Detector Based on a Chopping Amplifier in CMOS 65-nmNathan Seutin, Hugo Garcia-Vazquez, Alexandre Quenon, Fortunato Carlos Dualibe. 261-264 [doi]
- Design of a Quasi-Linear Rail-to-Rail Delay Element with an Extended Programmable RangeJordan Lee Gauci, Edward Gatt, Owen Casha, Giacinto De Cataldo, Ivan Grech, Joseph Micallef. 265-268 [doi]
- Optimizing Power Consumption vs. Linearization in CMFB Amplifiers with Source DegenerationC. Bauza, J. M. Sanchez-Chiva, Jordi Madrenas, Daniel Fernández. 269-272 [doi]
- A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy OperationHyun Kook Park, Tae-Woo Oh, Seong-Ook Jung. 273-276 [doi]
- A 1.6 GHz Non-overlap Clock Generation with Differential Clock Driver and Clock Level Shifters for GS/s Sampling Rate Pipeline ADCsHakan Cetinkaya, Ali Zeki, Alper Girgin, Enver Derun Karabeyoglu, Tufan Coskun Karalar. 277-280 [doi]
- A Preamplifier-discriminator circuit based on a Common Gate Feedforward TIA for fast time measurements using diamond detectorsAbderrahmane Ghimouz, Fatah Rarbi, Laurent Gallin-Martel, Olivier Rossetto. 281-284 [doi]
- Near field measurement bench and on-chip sensor for FTB stress propagation analysisYann Bacher, L. Quazzo, Nicolas Froidevaux, Henri Braquet, Gilles Jacquemod. 285-288 [doi]
- Tunable Floating-Point for Artificial Neural NetworksMarta Franceschi, Alberto Nannarelli, Maurizio Valle. 289-292 [doi]
- Performance Improvement of a 2.4-GHz Multi-stage Rectifier Using Power Optimized WaveformsViet-Duc Pham, Hakim Takhedmit, Laurent Cirio. 293-296 [doi]
- Power Efficient Optimization Procedure for Asynchronous Electrostatic GeneratorsSeyed Hossein Daneshvar, Mohammad Maymandi-Nejad, Mehmet Rasit Yuce, Jean-Michel Redoute. 297-300 [doi]
- Mechanical Solution for Out-of-Plane Sensitivity Enhancement of CMOS MEMS Convective AccelerometersS. Abdellatif, Brahim Mezghani, F. Tounsi, Frédérick Mailly, Pascal Nouet. 301-304 [doi]
- Study and Design of MEMS Cross-Shaped Piezoelectric Vibration Energy HarvestersAbdul Hafiz Alameh, Mathieu Gratuze, Alexandre Robichaud, Frederic Nabki. 305-308 [doi]
- Miniaturized onboard electronics for attitude measurement of medium caliber projectilesF. Saada, A. Zeiner, K. Meder, L. Garcia-Gamez, L. Bernard. 309-312 [doi]
- Analysis and Design of a Passive Sliding IF Mixer With a Novel Built-in Gainstep Mechanism for an Integrated 2.4 GHz RF-ReceiverChristoph Beyerstedt, Vahid Bonehi, Tobias Saalfeld, Markus Scholl, Ralf Wunderlich, Stefan Heinen. 313-316 [doi]
- A 7th Derivative Gaussian Pulse Generator for IR-UWB Radar Applications in Pedestrian DetectionXin An, Jens Wagner, Frank Ellinger. 317-320 [doi]
- A Novel Cross-shaped Bandpass Filter with Reconfigurable Notch BandTeng Cheng, Sut-Kam Ho, Kam-Weng Tam, Wai Wa Choi, Guang-Hua Yang. 321-324 [doi]
- Preamble based SNR estimation for IEEE 802.15.4g MR-OFDMAmani Aloui, Ons Ben Rhouma, Chiheb Rebai. 325-328 [doi]
- 2.4 GHz Reconfigurable Low Voltage and Low Power VCO dedicated to Sensor Networks ApplicationsT. First, Andre A. Mariano, P. C. Lacerda, G. Brante, O. C. Gouveia Filho, Bernardo Leite. 329-332 [doi]
- An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners VariationsJigme Zangpo, Ricardo Povoa, Jorge Guilherme, Nuno Horta. 333-336 [doi]
- Ka-band MMIC Variable Gain Low Noise Amplifier for Electronic Scanning AntennaA. Lohou, D. Chaimbault, B. Lesur, A. Karas, Julien Lintignat, Bernard Jarry. 337-340 [doi]
- Miniature Dual Band Antenna for WPT applicationZahra Katbay, Rabie Jabasini, Mohammed Ismail, Ali Sibaie. 341-344 [doi]
- Energy Harvesting with 2.45 GHz Rectenna for urban applicationAchraf Waguaf, Romain Alvernhe, Ludivine Fadel, Marjorie Grzeskowiak. 345-348 [doi]
- A Single-Inductor Two-Step-Mixing Injection-Locked Frequency Divider by Four with Concurrent Tail-InjectionAlessandro Garghetti, Andrea L. Lacaita, Salvatore Levantino. 349-352 [doi]
- Car Radar Transceiver 80GHz Design Improvements Using EM-Cosimulation FlowGilles Montoriol, Piotr Kawka, Vincent Poisson. 353-356 [doi]
- Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient FaultsRafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen. 357-360 [doi]
- Use of Decoupling Cells for Mitigation of SET Effects in CMOS Combinational GatesMarko S. Andjelkovic, Milan Babic, Yuanqing Li, Oliver Schrape, Milos Krstic, Rolf Kraemer. 361-364 [doi]
- Exploring MAS to a High Level Abstration NoC Simulation EnvironmentGustavo L. Lima, Nelson de Farias Traversi, Diana F. Adamatti, Graçaliz Pereira Dimuro, Cristina Meinhardt, Eduardo Wenzel Brião, Odorico Machado Mendizabal. 365-368 [doi]
- Integrated ESOP Refactoring for Industrial DesignsWinston Haaswijk, Luca Gaetano Amarù, Patrick Vuillod, Jiong Luo, Mathias Soeken, Giovanni De Micheli. 369-372 [doi]
- A Self-Biased Schmitt Trigger for Low Power ApplicationsMohammed Al-Qadasi, Abdullah Alshehri, Talal Al-Attar, Hossein Fariborzi. 373-376 [doi]
- Design Space Exploration for Approximate Implementations of Arithmetic Data Path PrimitivesLukás Sekanina, Vojtech Mrazek, Zdenek Vasícek. 377-380 [doi]
- VerMI: Verification Tool for Masked ImplementationsVictor Arribas, Svetla Nikova, Vincent Rijmen. 381-384 [doi]
- Evaluation of Lattice-Based Signature Schemes in Embedded SystemsTim Güneysu, Markus Krausz, Tobias Oder, Julian Speith. 385-388 [doi]
- A 4-bit Architecture of SEED Block Cipher for IoT ApplicationsFilippos Pirpilidis, Lampros Pyrgas, Paris Kitsos. 389-392 [doi]
- Energy-efficient Masking of the Trivium Stream CipherMaxime Montoya, Thomas Hiscock, Simone Bacles-Min, Anca Molnos, Jacques J. A. Fournier. 393-396 [doi]
- Technology-agnostic power optimization for AES block cipherKais Chibani, Adrien Facon, Sylvain Guilley, Youssef Souissi. 397-400 [doi]
- Modeling of Stepped Air-Gap Ferrite Inductors in Switching Power SuppliesKateryna Stoyka, Giulia Di Capua, Nicola Femia. 401-404 [doi]
- Novel Approach to Modelling Electromechanical Coupling and Testing its Self-Consistency in Micro-Scale Kinetic Electromagnetic Energy HarvestersAndrii Sokolov, Dhiman Mallick, Saibal Roy, Michael Peter Kennedy, Elena Blokhina. 405-408 [doi]
- On 60 GHz Solid-State Transformers Designed in 65 nm CMOS TechnologyIgor M. Filanovsky. 409-412 [doi]
- High-Accuracy Wireless 6DOF Magnetic Tracking System Based on FEM ModelingA. Fernandez G. David, Enrico Macrelli, Danilo Demarchi, Marco Crepaldi. 413-416 [doi]
- Hysteretic Regulators with Partially-Saturated InductorsNicola Femia, Giulia Di Capua. 417-420 [doi]
- FTNoCSim: A new Simulation platform for Evaluating Network-on-Chip ReliabilityNassima Kadri, Ala-Eddine Yahiaoui, Mohamed Mehdi Kandi, Mouloud Koudil. 421-424 [doi]
- A Domain-specific Language for Automated Fault Injection in SystemC ModelsDouglas Lohmann, Alexis Huf, Djones Lettnin, Frank Siqueira, José Luís Güntzel. 425-428 [doi]
- A Novel Sizing Method Aiming Security Against Differential Power AnalysisVitor G. Lima, Plinio Finkenauer, Vinicius V. Camargo, Felipe S. Marques, Leomar R. Junior, Rafael Iankowski Soares. 429-432 [doi]
- The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic CircuitsMatheus F. Pontes, Paulo F. Butzen, Rafael B. Schvittz, S. Leomar Rosa, Denis Teixeira Franco. 433-436 [doi]
- Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMCMarwan Ammar, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria. 437-440 [doi]
- A Compact 5 GHz Lumped-Element Wilkinson Power Combiner on 28 nm Bulk CMOSMatthew Love, Mury Thian, Floris van der Wilt, Koen van Hartingsveldt, Kave Kianush. 441-444 [doi]
- A Broadband 13 Vpp 40% PAE Stacked Line Driver in 28 nm Bulk CMOSJan Cools, Thibaut Gurne, Patrick Reynaert. 445-448 [doi]
- Wide-band Active Tunable Phase Shifter Using Improved Non-Foster circuitSaadou Al Mokdad, Raafat Lababidi, Marc Le Roy, Sawsan Sadek, André Pérennec, Denis Le Jeune. 449-452 [doi]
- Automated Synthesis of 1.5-5 GHz SiGe BiCMOS Differential Amplifiers Loaded on Resistive and Complex-Impedance TerminationsAndrey A. Kokolov, Leonid I. Babak, Dmitriy A. Zhabin, Feodor I. Sheyerman, Alexey V. Drozdov. 453-456 [doi]
- A Current Balanced Multi-Phase Class-D Amplifier for Wideband Supply ModulatorJiawen Hu, Liu Chen, Yifei Hu. 457-460 [doi]
- 80 GHz VCO with Slow-wave Coplanar Stripline Synthesized Differential InductorEkta Sharma, Emmanuel Pistono, Philippe Ferrari, Sylvain Bourdel. 461-464 [doi]
- A Highly Linear Ring Oscillator for VCO-based ADCs in 65-nm CMOSLeidy Mabel Alvero-Gonzalez, Eric Gutierrez, Luis Hernández. 465-468 [doi]
- A Fully Integrated Sub-GHz Inductor-less VCO with a Frequency DoublerNingcheng GaoDing, Jean-Francois Bousquet. 469-472 [doi]
- Current-reuse RF LC-VCO Design for Autonomous Connected ObjectsFayrouz Haddad, Imen Ghorbel, Wenceslas Rahajandraibe, Mourad Loulou, Abdelhalim Slimane. 473-476 [doi]
- Open Platform Systems Under Scrutiny: A Cybersecurity Analysis of the Device TreeDimitrios Tychalas, Michail Maniatakos. 477-480 [doi]
- Enabling Secure MPSoC Dynamic Operation through Protected CommunicationSiavoosh Payandeh Azad, Behrad Niazmand, Gert Jervan, Johanna Sepúlveda. 481-484 [doi]
- Machine Learning For Security: The Case of Side-Channel Attack Detection at Run-timeMaria Mushtaq, Ayaz Akram, Muhammad Khurram Bhatti, Maham Chaudhry, Muneeb Yousaf, Umer Farooq, Vianney Lapotre, Guy Gogniat. 485-488 [doi]
- DVFS as a Security Failure of TrustZone-enabled Heterogeneous SoCEl Mehdi Benhani, Lilian Bossuet. 489-492 [doi]
- Challenges and examples of in-situ memory content extraction techniquesFranck Courbon. 493-496 [doi]
- Ultra-Low Power Amplifiers for IoT NodesAlfio Dario Grasso, Salvatore Pennisi. 497-500 [doi]
- A Low Power CMOS gm-C Polyphase Filter for Low-IF GPS ReceiverSiamak Delshadpour. 501-504 [doi]
- Design of CMOS OTAs with Settling-Time ConstraintsGianluca Giustolisi, Gaetano Palumbo. 505-508 [doi]
- Current-mode Temperature Compensation for a Differential Logarithmic Amplifier in 180nm BiCMOSY. Wenger, B. Meinerzhagen, A. Ghazinour. 509-512 [doi]
- Slicing FIFOs for on-chip memory bandwidth exhaustionMattis Hasler, Robert Wittig, Emil Matús, Gerhard P. Fettweis. 513-516 [doi]
- Isolation-Safe Speculative Access Control for Hardware Transactional MemoryTomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura. 517-520 [doi]
- Memory-Aware Tiles Workload Balance through Machine-Learnt Complexity Reduction for HEVCIago Storch, Bruno Zatt, Luciano Volcan Agostini, Guilherme Corrêa, Daniel Palomino. 521-524 [doi]
- Hardware aspects of Long Short Term MemoryIoannis Kouretas, Vassilis Paliouras. 525-528 [doi]
- An Analysis and a Solution of False Conflicts for Hardware Transactional MemoryYuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura. 529-532 [doi]
- Computation of Topological Entropy of Finite Representations of MapsZbigniew Galias. 533-536 [doi]
- Analog-based Compressive Sensing of Multichannel Neural Signals: Systematic Design ApproachesFereidoon Hashemi Noshahr, Mohamad Sawan. 537-540 [doi]
- CNNs with bistable-like non-volatile memristors: a novel mem-computing paradigm for the IoT eraAlon Ascoli, I. Messaris, Ronald Tetzlaff, Leon O. Chua. 541-544 [doi]
- Modeling of Memristors Under Sinusoidal Excitations with Various FrequenciesBartlomiej Garda, Zbigniew Galias. 545-548 [doi]
- Accurate PCM Crosspoint Emulator and its Use on Eigenvalues CalculationAnastasios Petropoulos, Theodore Antonakopoulos. 549-552 [doi]
- Use of Magnetoresistive Random-Access Memory as Approximate Memory for Training Neural NetworksNicolas Locatelli, Adrien F. Vincent, Damien Querlioz. 553-556 [doi]
- Verilog-A model of ferroelectric memristors dedicated to neuromorphic designCharly Meyer, Andre Chanthbouala, Soren Boyn, Jean Tomas, Vincent Garcia, Manuel Bibes, Stephane Fusil, Julie Grollier, Sylvain Saïghi. 557-560 [doi]
- Metal Oxide Resistive Memory (OxRAM) and Phase Change Memory (PCM) as Artificial Synapses in Spiking Neural NetworksElisa Vianello, Denys R. B. Ly, Selina La Barbera, Thomas Dalgaty, N. Castellani, G. Navarro, G. Bourgeois, A. Valentian, E. Nowak, Damien Querlioz. 561-564 [doi]
- A Purely Digital Memristor Emulator based on a Flux-Charge ModelOscar Camps, Mohamed Moner Al Chawa, Carol de Benito, Miquel Roca, Stavros G. Stavrinides, Rodrigo Picos, Leon O. Chua. 565-568 [doi]
- Scene Context Classification with Event-Driven Spiking Deep Neural NetworksPablo Negri, Miguel Soto, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona. 569-572 [doi]
- Impact of Near-Threshold and Variability on 7nm FinFET XOR CircuitsFabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Reis. 573-576 [doi]
- 10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETsTalha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri. 577-580 [doi]
- Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic CellsLeonardo H. Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis. 581-584 [doi]
- High Density GC-eDRAM Design in 16nm FinFETAmir Shalom, Robert Giterman, Adam Teman. 585-588 [doi]
- Configurable Multi-Port Dynamic Bitcell with Internal Refresh MechanismRoman Golman, Robert Giterman, Adam Teman. 589-592 [doi]
- Kinetic Energy Harvesting for the IoT: Perspectives and Challenges for the Next DecadeDimitri Galayko, Armine Karami, Philippe Basset, Elena Blokhina. 593-596 [doi]
- Energy-Efficient Start-up Power Management for Batteryless Biomedical Implant DevicesKaung Oo Htet, Jinwei Zhao, Rami Ghannam, Hadi Heidari. 597-600 [doi]
- A Single-Inductor Dual-Ouput (SIDO) DC-DC Converter for Implantable Medical Devices in 180nm Standard CMOS ProcessPei-Chun Liao, Yi-Lun Chen, Po-Hung Chen. 601-604 [doi]
- A Clock Boosted Charge Pump with Reduced Rise TimeAndrea Ballo, Gianluca Giustolisi, Alfio Dario Grasso, Gaetano Palumbo. 605-608 [doi]
- Vector Matrix Multiplication Using Crossbar Arrays: A Comparative AnalysisHussein Assaf, Yvon Savaria, Mohamad Sawan. 609-612 [doi]
- Design and Synthesis of Arbitrary Group Delay Filters for Integrated Analog Signal ProcessingJoao Alberto de Franca Ferreira, Emilie Avignon-Meseldzija, Pietro Maris Ferreira, Philippe Bénabès. 613-616 [doi]
- Complex Ladder Filter RealizationsKenneth Martin. 617-620 [doi]
- Optimizing Performance of GPU Applications with SM Activity Divergence MinimizationZois-Gerasimos Tasoulas, Iraklis Anagnostopoulos. 621-624 [doi]
- MEMS-IC Optimization Considering Design Parameters and Manufacturing Variation from both Mechanical and Electrical SideFlorin Burcea, Andreas Herrmann, Bing Li, Helmut Graeb. 625-628 [doi]
- A Novel quasi-Newton with Momentum Training for Microwave Circuit Models using Neural NetworksShahrzad Mahboubi, Hiroshi Ninomiya. 629-632 [doi]
- Design-dependent Monitors Based on Delay Sensitivity TrackingJahnavi Kasturi Rangan, Nasim Pour Aryan, Lantao Wang, Jens Bargfrede, Christian Funke, Helmut Graeb. 633-636 [doi]
- Modeling the effect of strong magnetic field on n-type MOSFET in strong inversionD. V. Nguyen, L. Werling, C. Po, Norbert Dumas, Morgan Madec, Wilfried Uhring, Luc Hebrard, Latifa Fakri-Bouchet, J. Pascal, Y. Wadghiri. 637-640 [doi]
- Neural Network Autoencoder for Change Detection in Satellite Image Time SeriesEkaterina Kalinicheva, Jérémie Sublime, Maria Trocan. 641-642 [doi]
- Implementation of the Standardized Human Body Communications - A Feasibility StudyRemy Vauche, H. Bounaceur, S. Zerenini, Nicolas Dehaese, Jean Gaubert, Hervé Barthélemy, Valentin Gies. 643-644 [doi]
- Dry Electrode Materials for Electrocardiographic MonitoringY. Gan, Remy Vauche, J.-F. Pons, Wenceslas Rahajandraibe. 645-646 [doi]
- Comparison between Quadrature-modulation EPWM transmitters with a 90° and 180° hybrid in physical modelsTomoaki Morita, Yohtaro Umeda. 647-648 [doi]
- Study of Stochastic Invertible Multiplier DesignsKaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu. 649-650 [doi]
- Experiments of Electric Vehicle Cart Modeling, Calibration, and OptimizationHaruya Fujii, Lei Lin, Masahiro Fukui. 651-652 [doi]
- Power-amplifier-inserted Transversal Filter that Recovers Quantization Noise Power by CMOS RectifierYuto Tanaka, Yohtaro Umeda, Kyoya Takano. 653-654 [doi]
- Deep Residual Learning-based Reconstruction of Stacked Autoencoder RepresentationHonggui Li, Maria Trocan. 655-656 [doi]
- Real-Time LED Flicker Detection and Mitigation: Architecture and FPGA-ImplementationNicolai Behmann, Holger Blume. 657-658 [doi]
- Adaptive Compressed Sensing Image Reconstruction Using Binary Measurement MatricesAli Akbari, Marco Trevisi, Maria Trocan. 659-660 [doi]
- Fast Design of Reliable, Flexible and High-Speed AWGN architectures with High Level SynthesisYann Delomier, Bertrand Le Gal, Jérémie Crenne, Christophe Jégo. 661-664 [doi]
- Parallel Robust Absolute Orientation on FPGA for Vision and RoboticsNikolaos Dimou, Manolis I. A. Lourakis, George Lentaris, Dimitrios Soudris, Dionysios I. Reisis. 665-668 [doi]
- Underdetermined Direction of Arrival Estimation by Sum and Difference Composite Co-ArraySho Iwazaki, Koichi Ichige. 669-672 [doi]
- Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower BandwidthYuki Miyauchi, Haruki Mori, Tetsuya Youkawa, Kazuki Yamada, Shintato Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Atsuki Inoue. 673-676 [doi]
- Low-complexity feature extraction unit for "Wake-on-Feature" speech processingSimon Lecoq, Jean Le Bellego, Angel Gonzalez, Benoit Larras, Antoine Frappe. 677-680 [doi]
- A Wearable Sensor Node for Detecting Atrial Fibrillation Using Real-Time Digital Signal ProcessingTuukka Panula, Tero Hurnanen, Jarno Tuominen, Matti Kaisti, Juho Koskinen, Mikko Pänkäälä, Tero Koivisto. 681-684 [doi]
- Dual Ring Prototype Electronic System for the Small Animal Fast Insert for MRIRobert Becker, Alfred Buck, Volker Commichau, Diogo Di Calafiori, Günther Dissertori, Lubomir Djambazov, Afroditi Eleftheriou, Peter Fischer, Mikiko Ito, Parisa Khateri, Werner Lustermann, Josep F. Oliver, Christian Ritzer, Michael Ritzert, Ulf Roser, Markus Rudin, Ilaria Sacco, Paola Solevi, Charalampos Tsoumpas, Geoffrey Warnock, Bruno Weber, Matthias T. Wyss, Agnieszka Zagozdzinska-Bochenck. 685-688 [doi]
- Triplet-based Spike Timing Dependent Plasticity Circuit Design for three-terminal Spintronic SynapseBeomsang Yoo, Ki-Ryong Kim, Seong-Ook Jung. 689-692 [doi]
- A scalable and efficient digital signal processing system for real time biological spike detectionSafouane Noubir, Yannick Bornat, Bertrand Le Gal. 697-700 [doi]
- Towards self-powered and autonomous wearable glucose sensorSara S. Ghoreishizadeh, Despina Moschou, Dearbhla McBay, Carla Gonalez-Solino, Gorachand Dutta, Mirella Di Lorenzo, Ahmed Soltan. 701-704 [doi]
- A functionalized carbon nanotube based electronic nose for the detection of nerve agentsPierre S. Laquintinie, A. Sachan, J. F. Feller, Cyril Lahuec, M. Castro, Fabrice Seguin, Laurent Dupont. 705-708 [doi]
- A 7-Parameter Platform for Smart and Wireless Networks Monitoring On-Line Water QualityL. Mezzera, Marco Carminati, M. Di Mauro, A. Turolla, M. Tizzoni, M. Antonelli. 709-712 [doi]
- A Precise and Accurate Indoor Localization System based on Sub-Harmonic FMCW RadarNaglaa El Agroudy, Mohammed El-Shennawy, Niko Joram, Sami Ur Rehman, Frank Ellinger. 713-716 [doi]
- A Low-Power and Area-Efficient Digitally Controlled Shunt-Capacitor Delay Element for High-Resolution Delay LinesNico Angeli, Klaus Hofmann. 717-720 [doi]
- A Compact 6 ns Propagation Delay 200 Mbps 100 kV/µs CMR Capacitively Coupled Direction Configurable 4-Channel Digital Isolator in Standard CMOSGuangda Shi, Renhui Yan, Jianxiong Xi, Lenian He, Wanxin Ding, Wenjie Pan, Zhenqing Liu, Feng Yang, Dongpo Chen. 721-724 [doi]
- th-Order Continuous-Time $\Delta\Sigma$ Modulator with Improved Clock Jitter Immunity using RTZ FIR DACIan Assom, Gerardo Molina Salgado, Daniel O'Hare, Ivan O'Connell, Keith A. O'Donoghue. 725-728 [doi]
- ADC Resolution for Simultaneous Reception of Two Signals with High Dynamic RangeBaptiste Laporte-Fauret, Guillaume Ferré, Dominique Dallet, Bryce Minger, Loic Fuche. 729-732 [doi]
- Direct Digital Frequency Synthesis design methodology for optimized spurs / jitter performancesGregory Darcheville, Cyril Voillequin, Jean-Baptiste Begueret. 733-736 [doi]
- Digital Acquisition Chain for the Upgrade of the CERN SPS Beam Position MonitorIrene Degl'Innocenti, Luca Fanucci, Joel Albertone, Andrea Boccardi, Thierry Bogey, Carla Moran Guizan, Manoel Barros Marin, Athanasios Topaloudis, Manfred Wendt. 737-740 [doi]
- Hardware Implementation of A Chaotic Pseudo Random Number Generator Based on 3D Chaotic System without EquilibriumMaisam Jalilian, Arash Ahmadi, Majid Ahmadi. 741-744 [doi]
- An Efficient Approach for Neural Network ArchitectureKasem Khalil, Omar Eldash, Ashok Kumar 0001, Magdy Bayoumi. 745-748 [doi]
- Connected Component Analysis for Traffic Sign Recognition Embedded Processing SystemsFanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello. 749-752 [doi]
- Designing Fast Convolutional Engines for Deep Learning ApplicationsFanny Spagnolo, Stefania Perri, Fabio Frustaci, Pasquale Corsonello. 753-756 [doi]
- Exploring RSA Performance up to 4096-bit for Fast Security Processing on a Flexible Instruction Set Architecture ProcessorGrégory C. Marchesan, Nelson R. Weirich, Eduardo C. Culau, Iacana Ianiski Weber, Fernando Gehm Moraes, Everton Carara, Leonardo Londero de Oliveira. 757-760 [doi]
- Secure Admission of Applications in Many-coresLuciano L. Caimi, Vinicius Fochi, Fernando Gehm Moraes. 761-764 [doi]
- An Asynchronous Fixed Priority Arbiter for High througput Time Correlated Single Photon Counting SystemsTimothe Turko, Wilfried Uhring, Foudil Dadouche, Laurent Fesquet. 765-768 [doi]
- Simplified Deep-Learning-based decoders for linear block codesE. Kavvousanos, Vassilis Paliouras, Ioannis Kouretas. 769-772 [doi]
- Evaluating Serialization for a Publish-Subscribe Based Middleware for MPSoCsJean Carlo Hamerski, Anderson R. P. Domingues, Fernando Gehm Moraes, Alexandre M. Amory. 773-776 [doi]
- A Radix-4 Partial Product Generation-Based Approximate Multiplier for High-speed and Low-power Digital Signal ProcessingXiaoting Sun, Yi Guo, Zhenhao Liu, Shinji Kimura. 777-780 [doi]
- Using Bluetooth Low Energy to trigger an ultra-low power FSK wake-up receiverPaul Gavrikov, Pascal E. Verboket, Tolgay Ungan, Markus Muller, Matthias Lai, Christian Schindelhauer, Leonhard M. Reindl, Thomas Wendt. 781-784 [doi]
- Efficiency of Orthogonal Codes for Quasi-passive Wake-Up Radio Receivers using Frequency Footprint IDsMark S. Widmaier, Florin Hutu, Guillaume Villemaud. 785-788 [doi]
- Benefits of Joint Optimization of Tunable Wake-up Radio Architecture and ProtocolsMickael Maman, Dominique Morche, Baudouin Martineau, Clement Jany, Ivan Miro Panades, Anthony Quelen, Franck Badets, Edith Beigné. 789-792 [doi]
- Nanowatt Wake-Up Radios: Discrete-Components and Integrated ArchitecturesA. Elgani, M. Magno, F. Renzini, Luca Perilli, Eleonora Franchi Scarselli, Antonio Gnudi, Roberto Canegallo, G. Ricotti, Luca Benini. 793-796 [doi]
- Adaptive relaying for wireless sensor networks leveraging wake-up receiverNour El Hoda Djidi, Antoine Courtay, Matthieu Gautier, Olivier Berder. 797-800 [doi]
- Redundant SAR ADCs with Split-capacitor DACAntonio Lopez-Angulo, Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda. 801-804 [doi]
- Optimal NTF zero placement in MASH VCO-ADCs with higher order noise shapingEric Gutierrez, Luis Hernández, Susana Patón, Pieter Rombouts. 805-808 [doi]
- A Novel Multi-Bit Sigma-Delta Modulator using an Integrating SAR Noise-Shaped QuantizerRuben Garvi, Enrique Prefasi. 809-812 [doi]
- A Low-Power 2nd-Order Delta-Sigma ADC with an Inverter-Based Zero-Crossing DetectorDong-Jick Min, Sun Youl Choi, Jae Hoon Shim. 817-820 [doi]
- A 2.4GHz IEEE 802.15.6 Compliant 1.52nJ/bit TX & 1.32nJ/bit RX Multiband Transceiver for Low Power StandardsMustafijur Rahman, Ramesh Harjani. 821-824 [doi]
- Input Integrated Matching in RF LNA with Inductive Degeneration in Low-Power RegimeMichele Spasaro, Domenico Zito. 825-828 [doi]
- A Fast Switchable and Band-Tunable 5-7.5 GHz LNA in 45 nm CMOS SOI Technology for Multi-Standard Wake-up RadiosRui Ma, Martin Kreissig, Frank Ellinger. 829-832 [doi]
- A Study on Extending $f_{\mathrm{T}}$ in TIIMCA LNA TopologyAndreas Ely, Michele Spasaro, Domenico Zito. 833-836 [doi]
- Built-In Oscillation-Based Self-Testing of a 2.4 GHz LNA in 0.35µm CMOSHendrik P. Nel, Tinus Stander, Fortunato C. Dualibe. 837-840 [doi]
- Can Approximate Computing Reduce Power Consumption on FPGAs?Jorge Echavarria, Katja Schutz, Andreas Becher, Stefan Wildermann, Jürgen Teich. 841-844 [doi]
- Approximate Computing Methods for Embedded Machine LearningAli Ibrahim, Mario Osta, Mohamad Alameh, Moustafa Saleh, Hussein Chible, Maurizio Valle. 845-848 [doi]
- Quality-Scalable Approximate LMS FilterDarjn Esposito, Gennaro Di Meo, Davide De Caro, Antonio G. M. Strollo, Ettore Napoli. 849-852 [doi]
- Logic-In-Memory Architecture For Min/Max SearchMarco Vacca, Yaswanth Tavva, Anupam Chattopadhyay, Andrea Calimera. 853-856 [doi]
- Advances and Open Challenges for Integrated Circuits Detecting Bio-MoleculesMarco Carminati, Roland Thewes, Jacob K. Rosenstein, Hoi-Jun Yoo. 857-860 [doi]
- A VCO-based ADC with Relaxation Oscillator for Biomedical ApplicationsOlaitan Olabode, Antti Ontronen, Vishnu Unnikrishnan, Marko Kosunen, Jussi Ryynänen. 861-864 [doi]
- Current Mode Communication Scheme for Subretinal Implants with 8mV RMS Wire PotentialHenning Schutz, Denis Djekic, Stefan Gambach, Hans Kaim, Raphael Steinhoff, Albrecht Rothermel. 865-868 [doi]
- Autonomous readout ASIC with 169dB input dynamic range for amperometric measurementWei Onn Ting, Sara S. Ghoreishizadeh. 869-872 [doi]
- A Fully Integrated Fuzzy Logic Algorithm for Ischemic Heartbeat ClassificationGisela De La Fuente-Cortes, A. Díaz-Méndez, Victor R. Gonzalez-Diaz. 873-876 [doi]