Hyun-Kyu Yu - researchr alias

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Viewing Publication 1 - 17 from 17

2014

A 230ns settling time type-I PLL with 0.96mW TDC power and simple TV calculation algorithmJa-Yol Lee, Mi-Jeong Park, Hyun-Kyu Yu, Cheon-Soo Kim. mwscas 2014: 370-373 [doi]

2013

1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detectorSangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu. iet-cds, 7(3), 2013. [doi]

2012

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error CompensationJa-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu. tcas, 59-I(8):1706-1719, 2012. [doi]

2011

A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOSJaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho. isscc 2011: 176-178 [doi]

A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chipHoai-Nam Nguyen, Seung-Hwan Jung, Byung-Hun Min, Young Jae Lee, Sang-Gug Lee, Yun-Seong Eo, Hyun-Kyu Yu. esscirc 2011: 311-314 [doi]

2008

A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS TechnologyByung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu. jssc, 43(2):541-549, 2008. [doi]

2006

2005

Automatic tuning circuit for Gm-C filtersYoung-Ho Kim, Hyun-Kyu Yu. icecsys 2005: 1-4 [doi]

2004

2002

A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA)Kwang-Jin Koh, Yong-Sik Youn, Hyun-Kyu Yu. iscas 2002: 89-92 [doi]

A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulatorByung-Do Yang, Lee-Sup Kim, Hyun-Kyu Yu. iscas 2002: 373-376 [doi]

1999

A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technologyKeewook Jung, Changsik Yoo, Hyun-Kyu Yu, Wonchui Song, Wonchan Kim. tce, 45(1):171-175, 1999. [doi]

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