Table of Contents

• Analog design trends and challenges in 28 and 20nm CMOS technologyPierre Dautriche. 1-4 [doi]
• Circuit design in organic semiconductor technologiesPaul Heremans, Wim Dehaene, Michiel Steyaert, Kris Myny, Hagen Marien, Jan Genoe, Gerwin H. Gelinck, Erik van Veenendaal. 5-12 [doi]
• Photonics - Electronics integration on CMOSLaurent Fulbert, Jean-Marc Fedeli. 13-18 [doi]
• Brain-machine interfaces as the new frontier in extreme miniaturizationJan M. Rabaey. 19-24 [doi]
• Multimode-multiband transceivers for next generation of wireless communicationsAarno Pärssinen. 25-36 [doi]
• Wireless medical implant technology - Recent advances and future developmentsPeter D. Bradley. 37-41 [doi]
• DC-DC converters: From discrete towards fully integrated CMOSMichiel Steyaert, Tom Van Breussegem, Hans Meyvaert, Piet Callemeyn, Mike Wens. 42-49 [doi]
• High-k/metal gate innovations enabling continued CMOS scalingMartin M. Frank. 50-58 [doi]
• Fundamentals and current status of steep-slope tunnel field-effect transistorsAlan C. Seabaugh. 59-60 [doi]
• Current status on GaN-based RF-power devicesTetsuzo Ueda, Tsuyoshi Tanaka, Daisuke Ueda. 61-66 [doi]
• th order 9.6 GS/s FIR filter for high data rate 60-GHz wireless communicationsJonathan Müller, Bruno Stefanelli, Antoine Frappe, Lu Ye, Andreia Cathelin, Ali M. Niknejad, Andreas Kaiser. 67-70 [doi]
• A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequencePo-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen-Yi Lee. 71-74 [doi]
• Area- and energy-efficient high-throughput LDPC decoders with low block latencyMatthias Korb, Tobias G. Noll. 75-78 [doi]
• A 2.56 Gb/s soft RS (255, 239) decoder chip for optical communication systemsChih-Hsiang Hsu, Yi-Min Lin, Hsie-Chia Chang, Chen-Yi Lee. 79-82 [doi]
• A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOSAmit Agarwal, Steven Hsu, Sanu Mathew, Mark Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy. 83-86 [doi]
• A 3.4W digital-in class-D audio amplifierMarco Berkhout, Lutsen Dooper. 87-90 [doi]
• An audio 91-dB THD third-order fully-differential class-D amplifierDavide Cartasegna, Piero Malcovati, Lorenzo Crespi, Kyehyung Lee, Lakshmi Murukutla, Andrea Baschirotto. 91-94 [doi]
• Linearity and intrinsic gain enhancement techniques using positive feedbacks to realize a 1.2-V, 200-MHz, +10.3-dBm of IIP3 and 7th-order LPF in a 65-nm CMOSYasuhiro Sugimoto. 95-98 [doi]
• th-order CMOS complex filter for IEEE 802.15.4 standardAlberto Villegas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda. 99-102 [doi]
• A 1.6mW 0.5GHz open-loop VGA with fast startup and offset calibration for UWB radiosPieter Harpe, Cui Zhou, Kathleen Philips, Harmke de Groot. 103-106 [doi]
• A 100m-range 10-frame/s 340×96-pixel time-of-flight depth sensor in 0.18μm CMOSCristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Satoru Kato. 107-110 [doi]
• CMOS 3D image sensor based on pulse modulated time-of-flight principle and intrinsic lateral drift-field photodiode pixelsAndreas Spickermann, Daniel Durini, Andreas Suss, Wiebke Ulfig, Werner Brockherde, Bedrich J. Hosticka, Stefan Schwope, Anton Grabmaier. 111-114 [doi]
• A CMOS imager with digital phase readout for fluorescence lifetime imagingJian Guo, Sameer Sonkusale. 115-118 [doi]
• A 128-channel, 9ps column-parallel two-stage TDC based on time difference amplification for time-resolved imagingShingo Mandai, Edoardo Charbon. 119-122 [doi]
• A 140 dB equivalent dynamic range receiver interface for an infrared rain-sensing ICRainer Krenzke, Cang Ji. 123-126 [doi]
• A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTEJonas Fritzin, Christer Svensson, Atila Alvandpour. 127-130 [doi]
• A 31.5dBm outphasing class-D power amplifier in 45nm CMOS with back-off efficiency enhancement by dynamic power controlWei Tai, Hongtao Xu, Ashoke Ravi, Hasnain Lakdawala, Ofir B. Degani, L. Richard Carley, Yorgos Palaskas. 131-134 [doi]
• CMOS transformer-based uneven Doherty power amplifier for WLAN applicationsErcan Kaymaksut, Patrick Reynaert. 135-138 [doi]
• A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filterWagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels. 139-142 [doi]
• A 3-channel true-time delay transmitter for 60GHz radar-beamforming applicationsHugo Veenstra, Marc Notten, Dixian Zhao, John R. Long. 143-146 [doi]
• A 0.47-1.6mW 5bit 0.5-1GS/s time-interleaved SAR ADC for low-power UWB radiosPieter Harpe, Ben Busze, Kathleen Philips, Harmke de Groot. 147-150 [doi]
• A 7.65mW 5bits 90nm 1Gs/s ADC folded-interpolated without calibrationStefano D'Amico, Giuseppe Cocciolo, Marcello De Matteis, Andrea Baschirotto. 151-154 [doi]
• A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distributionWei-Hsiang Ma, Jerry C. Kao, Marios C. Papaefthymiou. 155-158 [doi]
• A 10 pJ/cycle ultra-low-voltage 32-bit microprocessor system-on-chipNathan Ickes, Yildiz Sinangil, Francesco Pappalardo 0002, Elio Guidetti, Anantha P. Chandrakasan. 159-162 [doi]
• Variation tolerant digitally assisted high-speed IO PHYEduard Roytman, Mali Nagarajan, Rahul Shah, Xin Ma, Ronald Bedard, Kambiz Munshi, Russell Iknaian, Fengxiang Cai, Jian Xu, Gayathri Sridharan Devi, Pradeep Vempada. 163-166 [doi]
• A 1.2-6 Gb/s, 4.2 pJ/bit Clock & Data Recovery circuit with high jitter tolerance in 0.14μm CMOSArnoud P. van der Wel, Gerrit den Besten. 167-170 [doi]
• A true single SoC for UHF mobile RFID readerJongmoon Kim, Seokoh Yun, Wonkap Oh, Minsu Kil, Sanghyun Cho. 171-174 [doi]
• An ultra-low power 400MHz OOK transceiver for medical implanted applicationsJunhua Liu, Chen Li, Long Chen, Yehui Xiao, Jiayi Wang, Huailin Liao, Ru Huang. 175-178 [doi]
• A 90nm CMOS UHF/UWB asymmetric transceiver for RFID readersJia Mao, David Sarmiento M., Qin Zhou, Jian Chen, Peng Wang, Zhuo Zou, Fredrik Jonsson, Li-Rong Zheng. 179-182 [doi]
• On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structureJinmyoung Kim, Toru Nakura, Hidehiro Takata, Koichiro Ishibashi, Makoto Ikeda, Kunihiro Asada. 183-186 [doi]
• A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOSSushrant Monga, Vinod Kumar. 187-190 [doi]
• 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domainsAtsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai. 191-194 [doi]
• Fast and robust level shifters in 65 nm CMOSGerhard Maderbacher, Thomas Jackum, Wolfgang Pribyl, Sylvia Michaelis, Dietrich Michaelis, Christoph Sandner. 195-198 [doi]
• A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIsYuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa. 199-202 [doi]
• Differential input topologies with immunity to electromagnetic interferenceFridolin Michel, Michiel Steyaert. 203-206 [doi]
• Analog baseband chain with analog to digital converter (ADC) of Synthetic Aperture Radar (SAR) receiverFaizah Abu Bakar, Tero Nieminen, Qaiser Nehal, Pekka Ukkonen, Ville Saari, Kari Halonen. 207-210 [doi]
• 2Björn Eversmann, Armin Lambacher, Thomas Gerling, Alexander Kunze, Peter Fromherz, Roland Thewes. 211-214 [doi]
• A stimulator ASIC with capability of neural recording during inter-phase delayXiao Liu, Andreas Demosthenous, Dai Jiang, Anne Vanhoestenberghe, Nick Donaldson. 215-218 [doi]
• A 0.5-V 1.13-μW/channel neural recording interface with digital multiplexing schemeWen-Sin Liew, Xiaodan Zou, Yong Lian. 219-222 [doi]
• 915-MHz wireless 64-channel neural recording SoC with programmable mixed-signal FIR filtersKarim Abdelhalim, Roman Genov. 223-226 [doi]
• A 1.95GHz sub-1dB NF, +40dBm OIP3 WCDMA LNA with variable attenuation in SiGe: C BiCMOSJos Bergervoet, Domine Leenaerts, Gerben W. de Jong, Edwin van der Heijden, Jan-Willem Lobeek, Alexander Simin. 227-230 [doi]
• Fully balanced low-noise transconductance amplifiers with P1dB > 0dBm in 45nm CMOSHemasundar Mohan Geddada, José Silva-Martínez, Stewart S. Taylor. 231-234 [doi]
• A 6.4mW, 1-3.5GHz current-mode receiver front-end with noise cancellationSaul Rodriguez Duenas, Ana Rusu. 235-238 [doi]
• A 200GHz downconverter in 90nm CMOSMaarten Tytgat, Michiel Steyaert, Patrick Reynaert. 239-242 [doi]
• Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelinesElie Maricau, Georges G. E. Gielen. 243-246 [doi]
• A failure-resilient xDSL line driver with on-chip degradation monitorPieter De Wit, Georges G. E. Gielen. 247-250 [doi]
• An aging suppression and calibration approach for differential amplifiers in advanced CMOS technologiesFlorian Chouard, Shailesh More, Michael Fulde, Doris Schmitt-Landsiedel. 251-254 [doi]
• Circuit-aware device reliability criteria methodologyJason T. Ryan, Lan Wei, Jason P. Campbell, Ricki G. Southwick, Kin P. Cheung, Anthony S. Oates, H.-S. Philip Wong, John Suehle. 255-258 [doi]
• A 4mW 1 GS/s continuous-time ΔΣ modulator with 15.6MHz bandwidth and 67 dB dynamic rangeAnkesh Jain, Muthusubramanian Venkateswaran, Shanthi Pavan. 259-262 [doi]
• th order subsampled RF ∑Δ ADC centered at 2.4GHz with a sine-shaped feedback DACAhmed Ashry, Hassan Aboushady. 263-266 [doi]
• 1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisitionFrancesco Cannillo, Enrique Prefasi, Luis Hernández, Ernesto Pun, Refet Firat Yazicioglu, Chris Van Hoof. 267-270 [doi]
• A 1.2 V 300 μW second-order switched-capacitor Δ∑ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOSBlazej Nowacki, Nuno F. Paulino, João Goes. 271-274 [doi]
• A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibrationKameswaran Vengattaramane, Jonathan Borremans, Michiel Steyaert, Jan Craninckx. 275-278 [doi]
• A precision DTMOST-based temperature sensorKamran Souri, Youngcheol Chae, Youri Ponomarev, Kofi A. A. Makinwa. 279-282 [doi]
• An energy-efficient 15-bit capacitive sensor interfaceZhichao Tan, Michiel A. P. Pertijs, Gerard C. M. Meijer. 283-286 [doi]
• A fully-digital, 0.3V, 270 nW capacitive sensor interface without external referencesHans Danneels, Kristof Coddens, Georges G. E. Gielen. 287-290 [doi]
• A charge balancing accelerometer interface with electrostatic dampingMikail Yücetas, Lasse Aaltonen, Mika Pulkkinen, Jarno Salomaa, Antti Kalanti, Kari Halonen. 291-294 [doi]
• Controlling the primary mode of gyroscopes with a phase-based amplitude regulationThomas Northemann, Rainer Schillinger, Michael Maurer, Yiannos Manoli. 295-298 [doi]
• A 1.6-2.6GHz 29dBm injection-locked power amplifier with 64% peak PAE in 65nm CMOSJonas Lindstrand, Carl Bryant, Markus Tormanen, Henrik Sjöland. 299-302 [doi]
• A fully integrated CMOS power amplifier for LTE-applications using clover shaped DATBrecht François, Patrick Reynaert. 303-306 [doi]
• A 11.4dBm 90nm CMOS H-Bridge resonating polar amplifier using RF Sigma Delta ModulationLiang Rong, Fredrik Jonsson, Li-Rong Zheng. 307-310 [doi]
• A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chipHoai-Nam Nguyen, Seung-Hwan Jung, Byung-Hun Min, Young Jae Lee, Sang-Gug Lee, Yun-Seong Eo, Hyun-Kyu Yu. 311-314 [doi]
• A high dynamic range fully-active 45-240MHz tunable RF bandpass filter for TV tunersSylvain Jolivet, Sébastien Amiot, Olivier Crand, Simon Bertrand, Bernard Jarry, Julien Lintignat. 315-318 [doi]
• A 36V voltage-to-current converter with dynamic element matching and auto-calibration for AC ripple reductionShagun Bajoria, Martijn F. Snoeij, Viola Schaffer, Mikhail V. Ivanov, Sijia Wang, Kofi A. A. Makinwa. 319-322 [doi]
• An analog readout circuit with offset calibration for cantiliver-based DNA detectionFausto Borghetti, Nicola Massari, David Stoppa, Andrea Adami, Leandro Lorenzelli, Franco Maloberti. 323-326 [doi]
• An area efficient multi-channel high side switch implementationAndrei Danchiv, Marian Hulub, Diana Manta. 327-330 [doi]
• A multi-frequency bioimpedance measurement ASIC for electrical impedance tomographyIasonas F. Triantis, Andreas Demosthenous, Mohamad Rahal, Hongwei Hong, Richard H. Bayford. 331-334 [doi]
• Active electrode IC combining EEG, electrical impedance tomography, continuous contact impedance measurement and power supply on a single wireMarco Guermandi, Roberto Cardu, Eleonora Franchi, Roberto Guerrieri. 335-338 [doi]
• A 0.5V 20fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical applicationSun-Il Chang, Khaled Al-Ashmouny, Euisik Yoon. 339-342 [doi]
• A 6Gbps 3mW optical receiver with DCOC-combined ATC in 65nm CMOSIppei Akita, Yuta Tsubouchi, Tetsuro Itakura, Michihiko Nishigaki, Hiroshi Uemura, Hideto Furuyama, Hideki Shibata. 343-346 [doi]
• An RF front-end for multi-channel direct RF sampling cable receiversOlivier Jamin, Vincent Rambeau, Franck Goussin, Guillaume Lebailly. 347-350 [doi]
• A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurementTae-Ho Kim, Jong-Seok Han, Sang-Soon Im, Jae-Young Jang, Jin-Ku Kang. 351-354 [doi]
• A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADCSunghyuk Lee, Anantha P. Chandrakasan, Hae-Seung Lee. 355-358 [doi]
• A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOSRay Nguyen, Christine Raynaud, Andreia Cathelin, Boris Murmann. 359-362 [doi]
• A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibrationU. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. 363-366 [doi]
• A 0.6-to-200MSPS speed reconfigurable and 1.9-to-27mW power scalable 10bit ADCHeng Zhang, Junhua Tan, Chao Zhang, Hongbo Chen, Edgar Sánchez-Sinencio. 367-370 [doi]
• A fully autonomous pulsed synchronous charge extractor for high-voltage piezoelectric harvestersThorsten Hehn, Dominic Maurath, Friedrich Hagedorn, Djordje Marinkovic, Ingo Kuehne, Alexander Frey, Yiannos Manoli. 371-374 [doi]
• A fast self-reacting capacitor-less low-dropout regulatorChia-Min Chen, Chung-Chih Hung. 375-378 [doi]
• A 350nA voltage regulator for 90nm CMOS digital circuits with Reverse-Body-BiasGerard Villar Pique, Maurice Meijer. 379-382 [doi]
• 55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converterTzu-Chi Huang, Wen-Shen Chou, Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Yung-Chow Peng, Fu-Lung Hsueh. 383-386 [doi]
• 3.1GHz-3.8GHz integrated transmission line super-regeneration amplifier with degenerative quenching technique for impulse-FM-UWB transceiverAli Zahabi, Muhammad Anis, Maurits Ortmanns. 387-390 [doi]
• A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADCMarco Sosio, Antonio Liscidini, Rinaldo Castello, Fernando De Bernardinis. 391-394 [doi]
• A fully digital delay-line based GHz-range multimode transmitter front-end in 65-nm CMOSPieter A. J. Nuyts, Peter Singerl, Franz Dielacher, Patrick Reynaert, Wim Dehaene. 395-398 [doi]
• A high frequency resolution Digitally-Controlled Oscillator using single-period switching schemeKazutoshi Kodama, Tetsuya Iizuka, Kunihiro Asada. 399-402 [doi]
• A low power all-digital signal component separator for uneven multi-level LINC systemsTsan-Wen Chen, Ping-Yuan Tsai, Dieter De Moitie, Jui-Yuan Yu, Chen-Yi Lee. 403-406 [doi]
• A monolithically-integrated optical receiver in standard 45-nm SOIMichael Georgas, Jason Orcutt, Rajeev J. Ram, Vladimir Stojanovic. 407-410 [doi]
• DC-DC converter assisted two-stage amplifier in organic thin-film transistor technology on foilHagen Marien, Michiel Steyaert, Erik van Veenendaal, Paul Heremans. 411-414 [doi]
• A tunable transconductor for analog amplification and filtering based on double-gate organic TFTsDaniele Raiteri, Fabrizio Torricelli, Eugenio Cantatore, Arthur H. M. van Roermund. 415-418 [doi]
• Current reference scheme for multilevel phase-change memory sensingAlessandro Cabrini, Fabio Gallazzi, Guido Torelli. 419-422 [doi]
• Post-silicon calibration of analog CMOS using phase-change memory cellsCheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li, Sangbum Kim, Jonathan Proesel, Chung Lam. 423-426 [doi]
• A 65-nm, 1-A buck converter with multi-function SAR-ADC-based CCM/PSK digital control loopSebastien Cliquennois, Achille Donida, Piero Malcovati, Andrea Baschirotto, Angelo Nagari. 427-430 [doi]
• Hybrid buck-linear (HBL) technique for enhanced dip voltage and transient response in load-preparation buck (LPB) converterChun-Jen Shih, Kuan-Yu Chu, Yu-Huei Lee, Ke-Horng Chen. 431-434 [doi]
• A single-inductor multiple-bipolar-output (SIMBO) converter with fully-adaptive feedback matrix and improved light-load rippleWeiwei Xu, Ye Li, Zhiliang Hong, Dirk Killat, Horst Schleifer. 435-438 [doi]
• A 3.3V 500mA digital Buck-Boost converter with 92% peak efficiency using constant ON/OFF time delta-sigma fractional-N controlQadeer Khan, Sachin Rao, Damian Swank, Arun Rao, William McIntyre, Sarvesh Bang, Pavan Kumar Hanumolu. 439-442 [doi]
• A constant off-time controlled boost converter with adaptive current sensing techniqueLin Cheng, Jinhua Ni, Zhiliang Hong, Bill Yang Liu. 443-446 [doi]
• A 0.06-psRMS SSC-induced jitter, ΔΣ-dithering-free, 6-GHz spread-spectrum clock generator for serial-ATA generationCheng-Liang Hung, Kuo-Hsing Cheng, Yu-Chen Lin, Bo-Qian Jiang, Che-hao Fan, Chi-Yang Chang. 447-450 [doi]
• A 300KHz bandwidth 3.9GHz 0.18μm CMOS fractional-N synthesizer with 13dB broadband phase noise reductionChun-Pang Wu, Sheng-Sian Wang, Hen-Wai Tsao, Jingshown Wu. 451-454 [doi]
• A 2.6psrms-period-jitter 900MHz all-digital fractional-N PLL built with standard cellsRichard Su, Steven Lanzisera, Kristofer S. J. Pister. 455-458 [doi]
• A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLsPing Lu, Pietro Andreani, Antonio Liscidini. 459-462 [doi]
• A 20-23GHz Coupled Oscillators Array in 65nm CMOS for HDR 60GHz beamforming applicationsMathieu Egot, Baudouin Martineau, Olivier Richard, Nathalie Rolland, Andreia Cathelin, Andreas Kaiser. 463-466 [doi]
• A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devicesDai Zhang, Ameya Bhide, Atila Alvandpour. 467-470 [doi]
• A 40nm 50S/s-8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generatorRyota Sekimoto, Akira Shikata, Tadahiro Kuroda, Hiroki Ishikuro. 471-474 [doi]
• A high energy-efficiency SAR ADC based on partial floating capacitor switching techniqueChien-Hung Kuo, Cheng-En Hsieh. 475-478 [doi]
• Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOSRobert C. N. Pilawa-Podgurski, David J. Perreault. 479-482 [doi]
• 2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOSHans Meyvaert, Tom Van Breussegem, Michiel Steyaert. 483-486 [doi]
• Automatic dead time optimization in a high frequency DC-DC buck converter in 65 nm CMOSGerhard Maderbacher, Thomas Jackum, Wolfgang Pribyl, Michael Wassermann, Andreas Petschar, Christoph Sandner. 487-490 [doi]
• A colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniquesLianming Li, Patrick Reynaert, Michiel Steyaert. 491-494 [doi]
• High-swing class-C VCOMassoud Tohidian, Ali Fotowat Ahmady, Mahmoud Kamarei, Fabien Ndagijimana. 495-498 [doi]
• A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swingWei Deng, Kenichi Okada, Akira Matsuzawa. 499-502 [doi]
• A scaled thermal-diffusivity-based frequency reference in 0.16μm CMOSMahdi Kashmiri, Kamran Souri, Kofi A. A. Makinwa. 503-506 [doi]
• A spread spectrum clock generator based on a short-term optimized chaotic mapFabio Pareschi, Gianluca Setti, Riccardo Rovatti, Giovanni Frattini. 507-510 [doi]
• Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOSFabio Sebastiano, Lucien J. Breems, Kofi A. A. Makinwa, Salvatore Drago, Domine Leenaerts, Bram Nauta. 511-514 [doi]
• An ultra low power bandgap operational at supply as low as 0.75VVadim Ivanov, Johannes Gerber, Ralf Brederlow. 515-518 [doi]
• A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data linkBram Rooseleer, Stefan Cosemans, Wim Dehaene. 519-522 [doi]
• A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refreshAnselme Vignon, Stefan Cosemans, Wim Dehaene. 523-526 [doi]
• -19Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto. 527-530 [doi]
• 8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodesVibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene. 531-534 [doi]
• A narrow-to-wideband scrambling technique increasing software radio receiver linearityFabian van Houwelingen, Ed van Tuijl, Bram Nauta, Maarten Vertregt. 535-538 [doi]
• Wideband 2 to 6GHz RF front-end with blocker filteringMikko Kaltiokallio, Ville Saari, Jussi Ryynänen, Sami Kallioinen, Aarno Pärssinen. 539-542 [doi]
• A 915MHz ultra-low power wake-up receiver with scalable performance and power consumptionXiongchuan Huang, Pieter Harpe, Guido Dolmans, Harmke de Groot. 543-546 [doi]
• A 65nm CMOS 282μW 915MHz direct conversion receiver front-endCarl Bryant, Henrik Sjöland. 547-550 [doi]
• A fully integrated high security NFC target IC using 0.18 μm CMOS processJong-Wook Lee, Duong Huynh Thai Vo, Sang Hoon Hong, Quoc-Hung Huynh. 551-554 [doi]