A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration

U. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. In Proceedings of the 37th European Solid-State Circuits Conference, ESSCIRC 2011, Helsinki, Finland, Sept. 12-16, 2011. pages 363-366, IEEE, 2011. [doi]

Abstract

Abstract is missing.