Abstract is missing.
- Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic AnalysisXiang-Dong Tan, C.-J. Richard Shi. 1-4 [doi]
- Symmetry Detection for Automatic Analog-Layout RecyclingYoucef Bourai, C.-J. Richard Shi. 5-8 [doi]
- An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated CircuitsHuazhong Yang, Rong Luo, Hui Wang, Runsheng Liu. 9 [doi]
- Relaxed Simulated Tempering for VLSI Floorplan DesignsJason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong. 13-16 [doi]
- Slicing Floorplans with Boundary ConstraintFung Yu Young, D. F. Wong. 17-20 [doi]
- Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro CellsXiaohai Wu, Changge Qiao, Xianlong Hong. 21 [doi]
- An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data CommunicationsJu-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee, Yong Jee. 25-28 [doi]
- A 10b 50 MHz CMOS A/D Converter for High-Speed Video ApplicationsByeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee, Sang-Won Yoon. 29-32 [doi]
- The Design of Delay Insensitive Asynchronous 16-bit MicroprocessorByung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee. 33-36 [doi]
- An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator SelectionShin ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta. 37-40 [doi]
- Motion Estimator LSI for MPEG2 High Level StandardLi Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda. 41-44 [doi]
- A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGCJin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee. 45-48 [doi]
- 16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular TelephonyTae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young-gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim. 49 [doi]
- Reduced-Order Modelling of Time-Varying SystemsJaijeet S. Roychowdhury. 53-56 [doi]
- Analysing Forced Oscillators with Multiple Time ScalesOnuttom Narayan, Jaijeet S. Roychowdhury. 57-60 [doi]
- Waveform Relaxation of Linear Integral-Differential Equations for Circuit SimulationYao-Lin Jiang, Omar Wing. 61-64 [doi]
- A New Technique to Exploit Frequency Domain Latency in Harmonic Balance SimulatorsMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney. 65 [doi]
- An Efficient Two-Level Partitioning Algorithm for VLSI CircuitsJong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho. 69-72 [doi]
- An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket StructuresC. K. Eem, J. W. Chong. 73-76 [doi]
- A Clustering Based Linear Ordering Algorithm for K-Way Spectral PartitioningShiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang. 77-80 [doi]
- Faster and Better Spectral Algorithms for Multi-Way PartitioningJan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang. 81 [doi]
- VCO Jitter Simulation and Its Comparison With MeasurementMasayuki Takahashi, Kimihiro Ogawa, Kenneth S. Kundert. 85-88 [doi]
- Enhancing the Efficiency of Reduction of Large RC networks By Pole Analysis via Congruence TransformationsHui Zheng, Wenjun Zhang, Lilin Tian, Zhilian Yang. 89-92 [doi]
- The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect CapacitanceJinsong Hou, Zeyi Wang, Xianlong Hong. 93 [doi]
- Interconnect Delay Estimation Models for Synthesis and Design PlanningJason Cong, David Zhigang Pan. 97-100 [doi]
- An Analytical Delay Model for SRAM-Based FPGA InterconnectionsFeng Zhou, Zhijun Huang, Jiarong Tong, PuShan Tang. 101-104 [doi]
- Timing-Driven Bipartitioning with Replication Using Iterative Quadratic ProgrammingShihliang Ou, Massoud Pedram. 105-108 [doi]
- An Integrated Battery-Hardware Model for Portable ElectronicsMassoud Pedram, Chi-Ying Tsui, Qing Wu. 109 [doi]
- Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIsShinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka. 113-116 [doi]
- A New Single-Clock Flip-Clop for Half-Swing ClockingYoung-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung. 117-120 [doi]
- Optimal Evaluation Clocking of Self-Resetting Domino PipelinesKenneth Y. Yun, Ayoob E. Dooply. 121-124 [doi]
- Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay InsertionTomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani. 125 [doi]
- A Performance-Driven I/O Pin Routing AlgorithmDongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen. 129-132 [doi]
- An Automatic Router for the Pin Grid Array PackageShuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai. 133-136 [doi]
- Crosstalk Reduction by Transistor SizingTong Xiao, Malgorzata Marek-Sadowska. 137-140 [doi]
- A Technology-Independent Methodology of Placement Generation for Analog CircuitWai-chee Wong, Philip C. H. Chan, Wai-On Law. 141 [doi]
- Technnology Mapping for Low PowerChing-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang. 145-148 [doi]
- An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI RoutingMaolin Tang, Kamran Eshraghian, Hon Nin Cheung. 149-152 [doi]
- Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System SynthesisNagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri. 153-156 [doi]
- Node Sampling Technique to Speed Up Probability-Based Power Estimation MethodsHoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung. 157-160 [doi]
- Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing ApproachHidehisa Nagano, Takayuki Suyama, Akira Nagoya. 161-164 [doi]
- A New Numerical Method for Transient Noise Analysis of Nonlinear CircuitsMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney. 165-168 [doi]
- Low Power CMOS Off-Chip Drivers with Slew-rate DifferenceRung-Bin Lin, Jinq-Chang Chen. 169-172 [doi]
- Benchmark Circuits Improve the Quality of a Standard Cell LibraryRung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai. 173-176 [doi]
- Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction ExecutionTakashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi. 177-180 [doi]
- Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-PairKoichi Hatta, Shin ichi Wakabayashi, Tetsushi Koide. 181-184 [doi]
- Hazard-Free Synthesis and Decomposition of Asynchronous CircuitsRen-Der Chen, Jer Min Jou, Yeu-Horng Shiau. 185-188 [doi]
- Hierarchical Floorplan Design on the InternetJiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang. 189-192 [doi]
- A Scheduling Method for Synchronous Communication in the Bach Hardware CompilerRyoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada, Tetsuya Fujimoto, Takashi Kambe. 193 [doi]
- Electronics Development of Silicon Microdisplay for Virtual Reality ApplicationsP. W. Cheng, H. C. Huang. 197-200 [doi]
- High-Speed and Low-Power Real-Time Programmable Video Multi-Processor for MPEG-2 Multimedia Chip on 0.6µm TLM CMOS TechnologySeung Min Lee, Jin-Hong Chung, Mike Myung-Ok Lee. 201-204 [doi]
- A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet TransformJer Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang. 205-208 [doi]
- A New Pipelined Architecture for Fuzzy Color CorrectionJer Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau. 209 [doi]
- Watermarking Layout TopologiesEdoardo Charbon, Ilhami Torunoglu. 213-216 [doi]
- Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay ModelYouxin Gao, D. F. Wong. 217-220 [doi]
- New Multilevel and Hierarchical Algorithms for Layout Density ControlAndrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky. 221-224 [doi]
- Function Smoothing with Applications to VLSI LayoutRoss Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov. 225 [doi]
- Layout-based Logic Decomposition for Timing OptimizationYun-Yin Lian, Youn-Long Lin. 229-232 [doi]
- Timing Optimization of Logic Network Using Gate DuplicationChun-hong Chen, Chi-Ying Tsui. 233-236 [doi]
- Model Order Reduction of Large Circuits Using Balanced TruncationPayam Rabiei, Massoud Pedram. 237 [doi]
- Optimization of Linear Placements for Wirelength Minimization with Free SitesAndrew B. Kahng, Paul Tucker, Alexander Zelikovsky. 241-244 [doi]
- A New Global Routing Algorithm Independent Of Net OrderingHaiyun Bao, Xianlong Hong, Yici Cai. 245-248 [doi]
- A Timing-Driven Block Placer Based on Sequence Pair ModelGang Huang, Xianlong Hong, Changge Qiao, Yici Cai. 249-252 [doi]
- Recent Advances in Asynchronous Design MethodologiesKenneth Y. Yun. 253 [doi]
- Universal Switched-Current Integrator Blocks for SI Filter DesignJack L. Chan, Steve S. Chung. 261-264 [doi]
- An On-Chip Automatic Tuning Circuit using Integration Level ApproximationLee Sung-Dae, Jang Myung-Jun, Leex Won-Hyo. 265-268 [doi]
- A High Speed and Low Power Phase-Frequency Detector and Charge - pumpWon Hyo Lee, Jun Dong Cho, Sung Dae Lee. 269-272 [doi]
- A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGCJin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee. 273 [doi]
- Data Path Synthesis for BIST with Low Area OverheadXiaowei Li, Paul Y. S. Cheung. 275-278 [doi]
- Testing Interconnects of Dynamic Reconfigurable FPGAsChi-Feng Wu, Cheng-Wen Wu. 279-282 [doi]
- Diagnosing Single Faults for Interconnects in SRAM Based FPGAsYinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi. 283-286 [doi]
- An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuitsHafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya. 287 [doi]
- A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit PartitionKai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi. 291-294 [doi]
- Estimation of Peak Current through CMOS VLSI Circuit Supply LinesToshio Murayama, Kimihiro Ogawa, Haruhiko Yamaguchi. 295-298 [doi]
- Power Consumption in XOR-Based CircuitsYibin Ye, Kaushik Roy, Rolf Drechsler. 299-302 [doi]
- Exploiting Don t Caers During Data Sequencing using Genetic AlgorithmsRolf Drechsler, Nicole Drechsler. 303 [doi]
- An Efficient Structural Approach to Board Interconnect DiagnosisChun-Keung Lo, Philip C. H. Chan. 307-310 [doi]
- On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent FaultsJin Ding, Yu-Liang Wu. 311-314 [doi]
- Combining GAs and Symbolic Methods for High Quality Tests of Sequential CircuitsMartin Keim, Nicole Drechsler, Bernd Becker. 315-318 [doi]
- Formal Verification Method for Combinatorial Circuits at High Level DesignJunji Kitamichi, Hiroyuki Kageyama, Nobuo Funabiki. 319 [doi]
- Minimization of Free BDDsWolfgang Günther, Rolf Drechsler. 323-326 [doi]
- Application Driven Variable Reordering and an Example Implementation in Reachability AnalysisChristoph Meinel, Klaus Schwettmann, Anna Slobodová. 327-330 [doi]
- Realization of Regular Ternary Logic FunctionsYukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno. 331 [doi]
- A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal ProcessingNozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki. 335-338 [doi]
- Generation of Interpretive and Compiled Instruction Set SimulatorsRainer Leupers, Johann Elste, Birger Landwehr. 339-342 [doi]
- Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional BehaviorsApostolos A. Kountouris, Christophe Wolinski. 343-346 [doi]
- Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design EnvironmentMarcello Lajolo, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 347 [doi]
- A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based DesignsWen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu. 351-354 [doi]
- A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph OptimizationBirger Landwehr. 355-358 [doi]
- Fast Boolean Matching Under Permutation Using RepresentativeDebatosh Debnath, Tsutomu Sasao. 359-362 [doi]
- FSM Modeling of Synchronous VHDL Design for Symbolic Model CheckingJinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong. 363 [doi]