Chein-Wei Jen - researchr alias

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Viewing Publication 1 - 70 from 70

2007

Latency-Tolerant Virtual Cluster Architecture for VLIW DSPPi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen. iscas 2007: 3506-3509 [doi]

2006

2005

A memory-efficient realization of cyclic convolution and its application to discrete cosine transformHun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen. tcsv, 15(3):445-453, 2005. [doi]

The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving PartitioningHun-Chen Chen, Tian-Sheuan Chang, Jiun-In Guo, Chein-Wei Jen. ieicet, 88-C(5):1061-1069, 2005. [doi]

Pipelining technique for energy-aware datapathsWei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen. iscas 2005: 1218-1221 [doi]

Architecture for area-efficient 2-D transform in H.264/AVCYu-Ting Kuo, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen. icmcs 2005: 1126-1129 [doi]

A multisymbol context-based arithmetic coding architecture for MPEG-4 shape codingKun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen. tcsv, 15(2):283-295, 2005. [doi]

An Efficient Quality-Aware Memory Controller for Multimedia Platform SoCKun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen. tcsv, 15(5):620-633, 2005. [doi]

A unified processor architecture for RISC & VLIW DSPTay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen. glvlsi 2005: 50-55 [doi]

Hierarchical instruction encoding for VLIW digital signal processorsChia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen. iscas 2005: 3503-3506 [doi]

2004

Trace-path analysis and performance estimation for multimedia application in embedded systemNelson Yen-Chung Chang, Kun-Bin Lee, Chein-Wei Jen. iscas 2004: 129-132

QME: an efficient subsampling-based block matching algorithm for motion estimationKun-Bin Lee, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen. iscas 2004: 305-308

A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organizationKun-Bin Lee, Hui-Cheng Hsu, Chein-Wei Jen. iscas 2004: 777-780

A fast dual symbol context-based arithmetic coding for MPEG-4 shape codingKun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen. iscas 2004: 317-320

A bandwidth and memory efficient MPEG-4 shape encoderKun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen. aspdac 2004: 525-526 [doi]

Optimal frame memory and data transfer scheme for MPEG-4 shape codingKun-Bin Lee, Hao-Yun Chin, Nelson Yen-Chung Chang, Hui-Cheng Hsu, Chein-Wei Jen. tce, 50(1):342-348, 2004. [doi]

A compact DSP core with static floating-point unit & its microcode generationTay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen. glvlsi 2004: 57-60 [doi]

Static floating-point unit with implicit exponent tracking for embedded DSPHung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen. iscas 2004: 821-824

2003

A memory efficient realization of cyclic convolution and its application to discrete cosine transformHun-Chen Chen, Jiun-In Guo, Chein-Wei Jen. iscas 2003: 33-36 [doi]

Edge-preserving texture filtering for real-time renderingYuan-Chung Lee, Chein-Wei Jen. vc, 19(1):10-22, 2003. [doi]

Area-effective FIR filter design for multiplier-less implementationTay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen. iscas 2003: 173-176 [doi]

Coefficient optimization for area-effective multiplier-less FIR filtersTay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen. icmcs 2004: 125-128 [doi]

An Efficient VLIW DSP Architecture for Baseband ProcessingTay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen. iccd 2003: 307-312 [doi]

Performance evaluation of ring-structure register file in multimedia applicationsTay-Jyi Lin, Chin-Chi Chang, Tsung-Hsun Yang, Yu-Ming Chang, Chien-Hung Lin, Chen-Chia Lee, Hung-Yueh Lin, Chein-Wei Jen. icmcs 2004: 121-124 [doi]

High-speed and low-power split-radix FFTWen-Chang Yeh, Chein-Wei Jen. tsp, 51(3):864-874, 2003. [doi]

Generalized Earliest-First Fast Addition AlgorithmWen-Chang Yeh, Chein-Wei Jen. TC, 52(10):1233-1242, 2003. [doi]

2002

2001

2000

A simple processor core design for DCT/IDCTTian-Sheuan Chang, Chin-Sheng Kung, Chein-Wei Jen. tcsv, 10(3):439-447, 2000.

A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routersIlion Yi-Liang Hsiao, Chein-Wei Jen. iscas 2000: 387-390 [doi]

On-Line Polygon Refining Using a Low Computation Subdivision AlgorithmYuan-Chung Lee, Chein-Wei Jen. gmp 2000: 209-219 [doi]

Deferred lighting: a computation-efficient approach for real-time 3-D graphicsBor-Sung Liang, Wen-Chang Yeh, Yuan-Chung Lee, Chein-Wei Jen. iscas 2000: 657-660 [doi]

Computation-effective 3-D graphics rendering architecture for embedded multimedia systemBor-Sung Liang, Chein-Wei Jen. tce, 46(3):735-743, 2000. [doi]

Motion estimation using on-line arithmeticChing-Long Su, Chein-Wei Jen. iscas 2000: 683-686 [doi]

A high performance carry-save to signed-digit recoder for fused addition-multiplicationWen-Chang Yeh, Chein-Wei Jen. icassp 2000: 3259-3262 [doi]

High-Speed Booth Encoded Parallel Multiplier DesignWen-Chang Yeh, Chein-Wei Jen. TC, 49(7):692-701, 2000. [doi]

1999

Bus buffer modeling and optimization in video processing IPKun-Bin Lee, Chia-Hsing Lin, Chein-Wei Jen. icecsys 1999: 1779-1782 [doi]

1998

Low power FIR filter realization with differential coefficients and inputTian-Sheuan Chang, Chein-Wei Jen. icassp 1998: 3009-3012 [doi]

An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth RequirementJen-Chien Tuan, Chein-Wei Jen. glvlsi 1998: 152-156 [doi]

1996

A programmable concurrent video signal processorChih-Chin Chen, Chein-Wei Jen. In ICIP (2). 1996: 1039-1042 [doi]

VASS - A VLSI array system synthesizerJinn-Wang Yeh, Wen-Jiunn Cheng, Chein-Wei Jen. vlsisp, 12(2):135-158, 1996. [doi]

1995

Scalable array architecture design for full search block matchingShifan Chang, Juin-Haur Hwang, Chein-Wei Jen. tcsv, 5(4):332-343, 1995. [doi]

1994

A motion detection scheme for motion adaptive pro-scan conversionShifan Chang, Chein-Wei Jen, Charng Long Lee. spic, 6(4):349-356, 1994. [doi]

A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley TransformJiun-In Guo, Chi-Min Liu, Chein-Wei Jen. iscas 1994: 235-238

A novel VLSI array design for the discrete Hartley transform using cyclic convolutionJiun-In Guo, Chi-Min Liu, Chein-Wei Jen. icassp 1994: 501-504 [doi]

1993

1992

1991

A high-level synthesizer for VLSI array architectures dedicated to digital signal processingTung-Hao Huang, Chi-Min Liu, Chein-Wei Jen. icassp 1991: 1221-1224 [doi]

1990

Recursive algorithms for AR spectral estimation and their array realizationsChi-Min Liu, Chein-Wei Jen. asap 1990: 121-132 [doi]

Parallel adaptive algorithm for moving target indicator and its VLSI array realizationChi-Min Liu, Bor-Shyong Yang, Chein-Wei Jen. icassp 1990: 1795-1798 [doi]

1989

Two-level pipeline design for image resamplingChein-Wei Jen, Chi-Min Liu. icassp 1989: 2441-2444 [doi]

Multi-dimensional parallel computing structures for regular iterative algorithmsChein-Wei Jen, Ding-Ming Kwai. integration, 8(3):331-340, 1989. [doi]

1986

Real-Time Configuration for Fault-Tolerant VLSI Array ProcessorsSun-Yuan Kung, Chih-Wei Jim Chang, Chein-Wei Jen. rtss 1986: 46-54

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