Table of Contents

• Future Management of the Semiconductor Manufacturing ProcessJames T. Healy. 10
• Plug and Play or Plug and Pray: We Have a Right to Know It Will Work (Or Why It Won t)Colin Maunder. 11
• Transient Power Supply Voltage (V::DDT::) Analysis for Detecting IC DefectsEdward I. Cole Jr., Jerry M. Soden, Paiboon Tangyunyong, Patrick L. Candelaria, Richard W. Beegle, Daniel L. Barton, Christopher L. Henderson, Charles F. Hawkins. 23-31
• i::DD:: Pulse Response Testing Applied to Complex CMOS ICsJ. S. Beasley, S. Pour-Mozafari, D. Huggett, Alan W. Righter, C. J. Apodaca. 32-39
• Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal DataJames F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan. 40-49
• A Low-Overhead Design for Testability and Test Generation Technique for Core-Based SystemsIndradeep Ghosh, Niraj K. Jha, Sujit Dey. 50-59
• Modifying User-Defined Logic for Test Access to Embedded CoresBahram Pouya, Nur A. Touba. 60-68
• An IEEE 1149.1-Based Test Access Architecture for ICs with Embedded CoresLee Whetsel. 69-78
• An Efficient Method for Compressing Test DataTakahiro J. Yamaguchi, Masahiro Ishida, Marco Tilgner, Dong Sam Ha. 79-88
• Hardware Compression Speeds on Bitmap Fail DisplayRobert Gage, Ben Brown, John Donaldson, Alexander Joffe. 89-93
• Low-Cost ATE PinElectronics for Multigigabit-per-Second At-Speed TestDavid C. Keezer, R. J. Wenzel. 94-100
• A Simulation-Based JTAG ATPG Optimized for MCMsAndrew Flint. 101-105
• Testing the 400-MHz IBM Generation-4 CMOS ChipThomas G. Foote, Dale E. Hoffman, William V. Huott, Timothy J. Koprowski, Bryan J. Robbins, Mary P. Kusko. 106-114
• Testing the Enterprise IBM System/390:::TM::: Multi ProcessorOtto A. Torreiter, Ulrich Baur, Georg Goecke, Kevin Melocco. 115-123
• Capacitive Leadframe TestingTed T. Turner. 124
• Analog AC Harmonic Method for Detecting Solder OpensChuck Robinson. 125-126
• Experiences with Implementation of I::DDQ:: Test for Identification and Automotive ProductsRalf Arnold, Markus Feuser, Horst-Udo Wedekind, Thorsten Bode. 127-135
• I::DDQ:: Characterization in Submicron CMOSAntoni Ferré, Joan Figueras. 136-145
• Intrinsic Leakage in Low-Power Deep Submicron CMOS ICsAli Keshavarzi, Kaushik Roy, Charles F. Hawkins. 146-155
• Current Signatures: ApplicationAnne E. Gattiker, Wojciech Maly. 156-165
• 1149.5: Now It s a Standard, So What?Harry Hulvershorn. 166-173
• IEEE P1149.4-Almost a StandardAdam Cron. 174-182
• Analog and Mixed-Signal Benchmark Circuits-First ReleaseBozena Kaminska, Karim Arabi, I. Bell, José L. Huertas, B. Kim, Adoración Rueda, Mani Soma, Prashant Goteti. 183-190
• Test Requirements for Embedded Core-Based Systems and IEEE P1500Yervant Zorian. 191-199
• A 256Meg SDRAM BIST for Disturb Test ApplicationTheo J. Powell, Dan Cline, Francis Hii. 200-208
• Cell Signal Measurement for High-Density DRAMsJörg E. Vollrath. 209-216
• A Self-Test Circuit for Evaluating Memory Sense-Amplifier SignalR. Dean Adams, Edmond S. Cooley, Patrick R. Hansen. 217-225
• The Implementation of Pseudo-Random Memory Tests on Commercial Memory TestersA. J. van de Goor, Mike Lin. 226-235
• Testability Enhancement for Behavioral Descriptions Containing Conditional StatementsKelly A. Ockunzzi, Christos A. Papachristou. 236-245
• Addressing Early Design-For-Test Synthesis in a Production EnvironmentVivek Chickermane, Kamran Zarrineh. 246-255
• A Symbolic Simulation-Based ANSI/IEEE Std 1149.1 Compliance Checker and BSDL GeneratorHarbinder Singh, James Beausang, Girish Patankar. 256-264
• H-SCAN+: A Practical Low-Overhead RTL Design-for-Testability Technique for Industrial DesignsToshiharu Asaka, Masaaki Yoshida, Subhrajit Bhattacharya, Sujit Dey. 265-274
• RF Introduction and Analog Junction Techniques for Finding OpensB. Karen McElfresh. 275
• Unpowered Opens Test with X-Ray LaminographyStig Oresjo. 276
• Finding Opens with OpticsDouglas W. Raymond. 277
• Manufacturing Pattern Development for the Alpha 21164 MicroprocessorCarol Stolicny, Richard Davies, Pamela McKernan, Tuyen Truong. 278-285
• Design of Cache Test Hardware on the HP PA8500Jeff Brauch, Jay Fleischman. 286-293
• Pentium:::®::: Pro Processor Design for Test and DebugAdrian Carbine, Derek Feltham. 294-303
• The Application of Novel Failure Analysis Techniques for Advanced Multi-Layered CMOS DevicesYeoh Eng Hong, Martin Tay Tiong We. 304-309
• Signature Analysis for IC Diagnosis and Failure AnalysisChristopher L. Henderson, Jerry M. Soden. 310-318
• Application and Analysis of IDDQ Diagnostic SoftwarePhil Nigh, Donato Forlenza, Franco Motika. 319-327
• Test Width Compression for Built-In Self TestingKrishnendu Chakrabarty, Jian Liu, Minyao Zhu, Brian T. Murray. 328-337
• On Using Machine Learning for Logic BISTChristophe Fagot, Patrick Girard, Christian Landrault. 338-346
• Using BIST Control for Pattern GenerationGundolf Kiefer, Hans-Joachim Wunderlich. 347-355
• ASIC Manufacturing Test Cost Prediction at Early Design StageVon-Kyoung Kim, Tom Chen, Mick Tegethoff. 356-361
• Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental StudyAdit D. Singh, Phil Nigh, C. Mani Krishna. 362-369
• A Low-Cost Massively-Parallel Interconnect Test Method for MCM SubstratesK. E. Newman, David C. Keezer. 370-378
• Dynamic Testing of ADCs Using Wavelet TransformsTakahiro J. Yamaguchi, Mani Soma. 379-388
• A Simplified Polynomial-Fitting Algorithm for DAC and ADC BISTStephen K. Sunter, Naveena Nagi. 389-395
• Signal Generation Using Periodic Single-and Multi-Bit Sigma-Delta Modulated StreamsBenoit Dufort, Gordon W. Roberts. 396-405
• Testability Features of AMD-K6:::TM::: MicroprocessorR. Scott Fetherston, Imtiaz P. Shaik, Siyad C. Ma. 406-413
• Next-Generation PowerPC:::TM::: Microprocessor Test Strategy ImprovementsCarol Pyron, Javier Prado, James Golab. 414-423
• A Case Study of the Test Development for the 2nd Generation ColdFire® MicroprocessorsMichael Mateja, Alfred L. Crouch, Renny Eisele, Grady Giles, Dale Amason. 424-432
• Logic Diagnosis-Diversion or Necessity?W. Kent Fuchs. 433
• Logical Diagnosis Solutions Must Drive Yield ImprovementPaul G. Ryan. 434
• IC Diagnosis: Industry IssuesJerry M. Soden, Christopher L. Henderson. 435
• Design for Primitive Delay Fault TestabilityAngela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar. 436-445
• Scan Latch Design for Delay TestJacob Savir. 446-453
• Delay Testing with Clock Control: An Alternative to Enhanced ScanRamesh C. Tekumalla, Premachandran R. Menon. 454-462
• An On-Line Self-Testing Switched-Current IntegratorOsama K. Abu-Shahla, Ian M. Bell. 463-470
• On-Line Testable Logic Desgin for FPGA ImplementationA. L. Burress, Parag K. Lala. 471-478
• A Parameterized VHDL Library for On-Line TestingCharles E. Stroud, M. Ding, S. Seshadri, Ramesh Karri, I. Kim, S. Roy, S. Wu. 479-488
• Design, Fabrications and Use of Mixed-Signal IC Testability StructuresKenneth P. Parker, John E. McDermid, Rodney A. Browen, Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa. 489-498
• Parasitic Effect Removal for Analog Measurement in P1149.4 EnvironmentChauchin Su, Yue-Tsang Chen, Shyh-Jye Jou. 499-508
• Implementation of Mixed Current/Voltage Testing Using the IEEE P1149.4 InfrastructureJosé Machado da Silva, Ana C. Leão, José Silva Matos, José Carlos Alves. 509-517
• High-Performance Production Test Contractors for Fine-Pitch Integrated CircuitsJames J. Brandes. 518-526
• A New Probe Card Technology Using Compliant Microsprings:::TM:::Nicholas Sporck. 527-532
• The Search for the Universal Probe Card SolutionR. Dennis Bates. 533-538
• BIST-Based Diagnostics of FPGA Logic BlocksCharles E. Stroud, Eric Lee, Miron Abramovici. 539-547
• Scan-Encoded Test Pattern Generation for BISTKun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski. 548-556
• To DFT or Not to DFT?Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly. 557-566
• The Fail-Stop Controller AE11Eberhard Böhl, Thomas Lindenkreuz, R. Stephan. 567-577
• Design and Realization of an Accurate Built-In Current Sensor for On-Line Power Dissipation Measurement and I::DDQ:: TestingKarim Arabi, Bozena Kaminska. 578-586
• On-Line Testing Scheme for Clock s FaultsCecilia Metra, Michele Favalli, Bruno Riccò. 587-596
• Oscillation and Sequential Behavior Caused by Interconnect Opens in Digital CMOS CircuitsHaluk Konuk, F. Joel Ferguson. 597-606
• Test Strategy Sensitivity to Defect ParametersMichel Renovell, Yves Bertrand. 607-616
• Fault Model Extension for Diagnosing Custom Cell FailsGilbert Vandling, Thomas Bartenstein. 617-624
• P1149.4-Problem or Solution for Mixed-Signal IC Design?Stephen K. Sunter. 625
• Optical Communication Channel Test Using BIST ApproachesMathieu Gagnon, Bozena Kaminska. 626-635
• System-Level Boundary-Scan in a Highly Integrated SwitchWilliam J. Hughes III. 636-639
• Analog Fault Diagnosis for Unpowered Circuit BoardsJiun-Lang Huang, Kwang-Ting Cheng. 640-648
• Board Level Automated Fault Injection for Fault Coverage and Diagnostic EfficiencyBret A. Stewart. 649-654
• Pin Margin AnalysisRobert E. Huston. 655-662
• Memory Test-Debugging Test Vectors Without ATESteve Westfall. 663-669
• A DSP-Based Feedback Loop for Mixed-Signal VLSI TestingLakshmikantha S. Prabhu, Daniel A. Rosenthal. 670-674
• OLDEVDTP: A Novel Environment for Off-Line Debugging of VLSI Device Test ProgramsYuhai Ma, Wanchun Shi. 675-684
• Incorporating Physical Design-for-Test into RoutingRichard McGowen, F. Joel Ferguson. 685-693
• Parameterizable Testing Scheme for FIR FiltersNilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer. 694-703
• An Efficient Scheme to Diagnose Scan ChainsSridhar Narayanan, Ashutosh Das. 704-713
• Scan Synthesis for One-Hot SignalsSubhasish Mitra, LaNae J. Avra, Edward J. McCluskey. 714-722
• Putting the Squeeze on Test SequencesElizabeth M. Rudnick, Janak H. Patel. 723-732
• Sequential Test Generation with Advanced Illegal State SearchM. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor. 733-742
• A Novel Functional Test Generation Method for Processors Using Commercial ATPGRaghuram S. Tupuri, Jacob A. Abraham. 743-752
• Testability Analysis and ATPG on Behavioral RT-Level VHDLFulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 753-759
• HABIST: Histogram-Based Analog Built-In Self-TestArnold Frisch, Thomas Almy. 760-767
• Experimental Results for Current-Based Analog ScanThomas M. Bocek, Tuyen D. Vu, Mani Soma, Jason D. Moffatt. 768-775
• On-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked LoopsBenoît R. Veillette, Gordon W. Roberts. 776-785
• Oscillation Built-In Self Test (OBIST) Scheme for Functional and Structural Testing of Analog and Mixed-Signal Integrated CircuitsKarim Arabi, Bozena Kaminska. 786-795
• Low Current and Low Voltages-The High-End OP AMP Testing ChallengeBob Cometta, Jan Witte. 796-801
• Real-Time In-situ Monitoring and Characterization of Production Wafer Probing ProcessMinh Quach, Kim Harper. 802-808
• Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal InputsWeiyu Chen, Melvin A. Breuer, Sandeep K. Gupta. 809-818
• How Seriously Do You Take Your Possible-Detect Faults?Rajesh Raina, Charles Njinda, Robert F. Molyneaux. 819-828
• ACT: A DFT Tool for Self-Timed CircuitsAjay Khoche, Erik Brunvand. 829-837
• BART: A Bridging Fault Test Generation for Sequential CircuitsJames P. Cusey, Janak H. Patel. 838-847
• DS-LFSR: A New BIST TPG for Low Heat DissipationSeongmoon Wang, Sandeep K. Gupta. 848-857
• Tree-Structured Linear Cellular Automata and Their Applications as PRPGsJ. Li, X. Sun, K. Soon. 858-867
• An Effective BIST Scheme for Arithmetic Logic UnitsDimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian, Mihalis Psarakis. 868-877
• Diagnosis of Bridging Faults in Sequential Circuits Using Adaptive Simulation, State Storage, and Path-TracingSrikanth Venkataraman, W. Kent Fuchs. 878-886
• Bridging Fault Diagnosis in the Absence of Physical InformationDavid B. Lavo, Tracy Larrabee, F. Joel Ferguson, Brian Chess, Jayashree Saxena, Kenneth M. Butler. 887-893
• Fault Diagnosis in Scan-Based BISTJanusz Rajski, Jerzy Tyszer. 894-902
• Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and DiagnosisRamakrishna Voorakaranam, Sudip Chakrabarti, Junwei Hou, Alfred V. Gomes, Sasikumar Cherubal, Abhijit Chatterjee, William H. Kao. 903-912
• Fault Macromodeling for Analog/Mixed-Signal CircuitsChen-Yang Pan, Kwang-Ting Cheng. 913-922
• Development of a MEMS Testing MethodologyAbhijeet Kolpekwar, Ronald D. Blanton. 923-931
• Embedded At-Speed Test ProbeMitch Aigner. 932-937
• An IDDQ Sensor Circuit for Low-Voltage ICsYukiya Miura. 938-947
• Supervisors for Testing Non-Deterministically Specified SystemsTony Savor, Rudolph E. Seviora. 948-953
• A New Validation Methodology Combining Test and Formal Verification for PowerPC:::TM::: Microprocessor ArraysLi-C. Wang, Magdy S. Abadir. 954-963
• Analyzing a PowerPC:::TM:::620 Microprocessor Silicon Failure Using Model CheckingRichard Raimi, James Lear. 964-973
• Error Tracer: A Fault-Simualtion-Based Approach to Design Error DiagnosisShi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng. 974-981
• Algorithms for Switch Level Delay Fault SimulationSoumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski. 982-991
• Efficient Identification of Non-Robustly Untestable Path Delay FaultsZhongcheng Li, Robert K. Brayton, Yinghua Min. 992-997
• Effective Path Selection for Delay Fault Testing of Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal. 998-1003
• Structuring STIL for Incremental Test DevelopmentGregory A. Maston. 1004-1010
• A Unified Interface for Scan Test Generation Based on STILPeter Wohl, John A. Waicukauski. 1011-1019
• Artificial Intelligence Exchange and Service Tie to All Test Environments (AI-ESTATE)-A New Standard for System DiagnosticsJohn W. Sheppard, Leslie A. Orlidge. 1020-1029
• Advances in Probe Technology: Best Sessions of the 97 Southwest Test WorkshopDave Unzicker, Michael Bonham, Rey Rincon. 1030
• Why Would an ASIC Foundry Accept Anything Less than Full Scan?Steven F. Oakland. 1031
• The Case of Partial ScanJeff Rearick. 1032
• Why Automate Optical Inspection?Douglas W. Raymond, Dominic F. Haigh. 1033
• Ethics, Professionalism and Accountability in TestingWilliam R. Simpson. 1034
• Vision Inspection: Meeting the Promise?Richard Pye. 1035
• Solder Paste Inspection: Process Control for Defect ReductionDonald Burr. 1036
• So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods ExperimentPhil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly. 1037-1038
• Thoughts on Core Integration and TestThomas L. Anderson. 1039
• Embedded Core Test Plug-n-Play: Is It Achievable?Rudy Garcia. 1040
• Test Access of TAP ed & Non-TAP ed CoresLee Whetsel. 1041
• On-Line Testing for VLSIMichael Nicolaidis. 1042
• Weak Write Test Mode: An SRAM Cell Stability Design for Test TechniqueAnne Meixner, Jash Banik. 1043-1052
• Just how real is the SIA roadmapWayne M. Needham. 1151 [doi]
• SIA Roadmap: test must not limit future technologiesPhil Nigh. 1152 [doi]
• How real is the new SIA roadmap for mixed-signal test equipment?William R. Ortner. 1153 [doi]
• The rise and fall of the ATE industryTodd E. Rockoff. 1154 [doi]
• Functional ATE can meet the challengesBurnell G. West. 1155 [doi]
• National Science Foundation Workshop on Future Research Directions in Testing of Electronic Circuits and Systems: executive summary of workshop reportKwang-Ting Cheng. 1157 [doi]
• Flying probe test systems: capabilities for effective testingJack Ferguson. 1163 [doi]
• The stuck-at fault: it ain t over til it s overKenneth M. Butler. 1165 [doi]
• Stuck-at fault: a fault model for the next millenniumKenneth M. Butler. 1166 [doi]
• Buying time for the stuck-at fault modelJeff Rearick. 1167 [doi]
• Current signatures: application [to CMOS]Anne E. Gattiker, Wojciech Maly. 1168-1177 [doi]