Abstract is missing.
- Macro-Based Hardware Compilation of Java(tm) Bytecodes into a Dynamic Reconfigurable Computing SystemJoão M. P. Cardoso, Horácio C. Neto. 2-11 [doi]
- A CAD Suite for High-Performance FPGA DesignBrad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting. 12-24 [doi]
- Formal Verification of Reconfigurable CoresSatnam Singh, Carl Johan Lillieroth. 25 [doi]
- Transmutable Telecom System and Its ApplicationToshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Atsushi Takahara. 34-43 [doi]
- Implementation and Evaluation of a Prototype Reconfigurable RouterJason R. Hess, David C. Lee, Scott J. Harper, Mark T. Jones, Peter M. Athanas. 44 [doi]
- Pipeline Vectorization for Reconfigurable SystemsMarkus Weinhardt, Wayne Luk. 52-62 [doi]
- Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory BanksMaya Gokhale, Janice M. Stone. 63-69 [doi]
- Parallelizing Applications into SiliconJonathan Babb, Martin C. Rinard, Csaba Andras Moritz, Walter Lee, Matthew Frank, Rajeev Barua, Saman P. Amarasinghe. 70 [doi]
- Reconfigurable Elements for a Video Pipeline ProcessorMichael R. Piacentino, Gooitzen S. van der Wal, Michael W. Hansen. 82-91 [doi]
- ConCISe: A Compiler-Driven CPLD-Based Instruction Set AcceleratorBernardo Kastrup, Arjan Bink, Jan Hoogerbrugge. 92 [doi]
- CPR: A Configuration Profiling ToolSrihari Cadambi, Seth Copen Goldstein. 104-113 [doi]
- Debugging Techniques for Dynamically Reconfigurable HardwareNicholas McKay, Satnam Singh. 114-122 [doi]
- Improving Simulation Accuracy in Design Methodologies for Dynamically Reconfigurable Logic SystemsMilan Vasilko, David Cabanis. 123 [doi]
- Reconfigurable Computing for Augmented RealityWayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung. 136-145 [doi]
- Sepia: Scalable 3D Compositing Using PCI PametteLaurent Moll, Mark Shand, Alan Heirich. 146 [doi]
- An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule CheckingZhen Luo, Margaret Martonosi, Pranav Ashar. 158-167 [doi]
- FAFNER-Accelerating Nesting Problems with FPGAsJosé Carlos Alves, João Canas Ferreira, C. Albuquerque, José F. Oliveira, J. Soeiro Ferreira, José Silva Matos. 168 [doi]
- Field Programmable Gate Array Based Radar Front-End Digital Signal ProcessingTyler J. Moeller, David R. Martinez. 178-187 [doi]
- Optimizing FPGA-Based Vector Product DesignsDan Benyamin, John D. Villasenor, Wayne Luk. 188 [doi]
- PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable ComputingRonald Laufer, R. Reed Taylor, Herman Schmit. 200-208 [doi]
- Safe and Protected Execution for the Morph/AMRM Reconfigurable ProcessorAndrew A. Chien, Jay H. Byun. 209-221 [doi]
- Implementing an API for Distributed Adaptive Computing SystemsMark Jones, Luke Scharf, Jonathan Scott, Chris Twaddle, Matthew Yaconis, Kuan Yao, Peter Athanas, Brian Schott. 222 [doi]
- A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key AlgorithmsGerardo Orlando, Christof Paar. 232-239 [doi]
- Automatic Floating to Fixed Point Translation and its Application to Post-Rendering 3D WarpingM. P. Leong, M. Y. Yeung, C. K. Yeung, C. W. Fu, P. A. Heng, Philip Heng Wai Leong. 240-248 [doi]
- Dynamic Precision Management for Loop Computations on Reconfigurable ArchitecturesKiran Bondalapati, Viktor K. Prasanna. 249 [doi]
- Accelerating Run-Time Reconfiguration on FCCMsJean-Paul Heron, Roger Woods. 260-261 [doi]
- A Virtual Hardware Handler for RTR SystemsRichard H. Turner, Roger Woods, Sakir Sezer, Jean-Paul Heron. 262-263 [doi]
- Algorithm Analysis and Mapping Environment for Adaptive Computing Systems: Further ResultsEric K. Pauer, Paul D. Fiore, John M. Smith. 264-265 [doi]
- Development System for FPGA-Based Digital CircuitsValery Sklyarov, J. Fonseca, Ricardo Sal Monteiro, Arnaldo Oliveira, Andreia Melo, Nuno Lau, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari. 266-267 [doi]
- Design of a JTAG Based Run Time Reconfigurable SystemCynthia Cousineau, François Laperle, Yvon Savaria. 268-269 [doi]
- Architectures for System-Level Applications of Adaptive ComputingBrian Schott, Chen Chen, Steve Crago, Joseph Czarnaski, Matt French, Ivan Hom, Tam Tho, Terri Valenti. 270-27 [doi]
- Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA ArchitecturesVinoo Srinivasan, Ranga Vemuri. 272 [doi]
- Enabling Automatic Module Generation for FCCM CompilersAndreas Koch. 274 [doi]
- ICARUS: A Dynamically Reconfigurable Computer ArchitectureMichael Baxter. 278 [doi]
- SONIC - A Plug-In Architecture for Video ProcessingSimon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone. 280-281 [doi]
- A Reconfigurable Platform for Academic PurposesChristof Teuscher, Jacques-Olivier Haenni, Héctor Fabio Restrepo, Eduardo Sanchez, Francisco J. Gómez. 282-283 [doi]
- VHDL Placement Directives for Parametric IP BlocksJames Hwang, Cameron Patterson, Sujoy Mitra. 284-285 [doi]
- Runlength Compression Techniques for FPGA ConfigurationsScott Hauck, William D. Wilson. 286 [doi]
- Accelerating an IR Automatic Target Recognition Application with FPGAsJack S. N. Jean, Xuejun Liang, Brian Drozd, Karen A. Tomko. 290-291 [doi]
- Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable HardwareBenjamin A. Levine, Senthil Natarajan, Chandra Tan, Danny Newport, Donald W. Bouldin. 292-293 [doi]
- Hybrid Data/Configuration Caching for Striped FPGAsDeepali Deshpande, Arun K. Somani, Akhilesh Tyagi. 294-295 [doi]
- On Reconfiguring Cache for ComputingHuesung Kim, Arun K. Somani, Akhilesh Tyagi. 296-297 [doi]
- Reconfigurable Pipelines in VLIW Execution UnitsRonald D. Williams, Brian D. Kuebert. 298-299 [doi]
- Fast Online Placement for Reconfigurable ComputingKiarash Barzagan, Majid Sarrafzadeh. 300 [doi]
- A Compact Fast Variable Key Size Elliptic Curve Cryptosystem CoprocessorLijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman. 304-305 [doi]
- A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable HardwareMiron Abramovici, José T. de Sousa. 306-307 [doi]
- Reducing Compilation Time of Zhong s FPGA-Based SAT SolverPak K. Chan, Mark J. Boyd, S. Goren, K. Klenk, V. Kodavati, R. Kundu, M. Margolese, J. Sun, K. Suzuki, E. Thorne, X. Wang, J. Xu, M. Zhu. 308-309 [doi]
- FPGA-Based Structures for On-Line FFT and DCTDannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor. 310-311 [doi]
- An FPGA-Based Fan Beam Image Reconstruction ModuleLuiz Maltar, Felipe M. G. França, Vladimir Castro Alves, Cláudio L. Amorim. 312-313 [doi]
- Be zier Curve Rendering on Virtex(tm)Donald MacVicar, Satnam Singh, Robert Slous. 314 [doi]