Abstract is missing.
- The Great ATE RobberyAndrew Rappaport. 18
- Progress in DFT: A Personal ViewBen Bennetts. 19-20
- Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related DefectsUwe Gläser, Uwe Hübner, Heinrich Theodor Vierhaus. 21-29
- A Small Test Generator for Large DesignsSandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy. 30-40
- Sequential Test Generation Based on Real-Value LogicKazumi Hatayama, Kazunori Hikone, Mitsuji Ikeda, Terumine Hayashi. 41-48
- An Instruction Sequence Assembling Methodology for Testing MicroprocessorsJaushin Lee, Janak H. Patel. 49-58
- High-Performance CMOS-Based VLSI Testers: Timing Control and CompensationJim Chapman. 59-67
- The Advanced Test System Architecture Provides Fast and Accurate Test for a High Resolution ADCAkinori Maeda. 68-75
- A VXI Driver-Sensor Instrument with Large Tester ArchitectureMatthew L. Fichtenbaum, Robert J. Muller. 76-83
- Design Verification of a High Density Computer Using IEEE 1149.1Wayne T. Daniel. 84-90
- IEEE 1149.1 Applied to Mixed TTL-ECL and Differential LogicJohn Andrews. 91-95
- Impact of Boundary Scan Design on Delay TestE. Kofi Vida-Torku. 96-105
- Is IEEE 1149.1 Boundary Scan Cost Effective: A Simple Case StudyBarry Caldwell, Tom Langford. 106-109
- Optimized BIST Strategies for Programmable Data Paths Based on Cellular AutomataJos van Sas, Francky Catthoor, Hugo De Man. 110-119
- Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift RegistersSybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski. 120-129
- Self-Test Scheduling with Bounded Test ExecutionAlbrecht P. Stroele. 130-139
- Can Concurrent Checkers Help BIST?Sandeep K. Gupta, Dhiraj K. Pradhan. 140-150
- I::DDQ:: Testing in CMOS Digital ASIC s - Putting it All TogetherRoger Perry. 151-157
- An Evaluation of I::DDQ:: Versus Conventional Testing for CMOS Sea-of-Gate IC sK. Sawada, S. Kayano. 158-167
- The Effectiveness of I::DDQ::, Functional and Scan Tests: How Many Fault Coverages Do We Need?Peter C. Maxwell, Robert C. Aitken, Vic Johansen, Inshen Chiang. 168-177
- Diagnostic Fault Simulation of Sequential CircuitsElizabeth M. Rudnick, W. Kent Fuchs, Janak H. Patel. 178-186
- Sequential Circuit Diagnosis Based on Formal Verification TechniquesGianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 187-196
- Sequential Redundancy Identification Using Verification TechniquesJohn Moondanos, Jacob A. Abraham. 197-205
- A Proposed Method of Accessing 1149.1 in a Backplane EnvironmentLee Whetsel. 206-216
- A Boundary Scan Test Controller for Hierarchical BISTJosé M. M. Ferreira, Filipe S. Pinto, José Silva Matos. 217-223
- Boundary Scan Testing for Multichip ModulesStephen C. Hilla. 224-231
- Macro Testability: The Results of Production Device ApplicationsFrank Bouwman, Steven Oostdijk, Rudi Stans, Ben Bennetts, Frans P. M. Beenker. 232-241
- CCD Image Sensor Test Using Cellular Automation-Type Pattern Recognition SystemHaruo Kato. 242-246
- Correlation of Capacitive Load DelayRan Edeleman, Ishai Kreiser. 247-252
- MCM Test Using Available TechnologyDavid C. Keezer. 253
- Time-to-Market: An Issue in Mixed-signal vs. AnalogueKeith Baker. 254
- Does Object-Oriented Programming Fit in the Real World of ATE?Richard S. Levy. 255-256
- The Reality of Object Oriented Solutions for ATEJames R. Ward. 257-258
- COM (Cost Oriented Memory) TestingT. Yamada, Akihiro Fujiwara, Michiko Inoue. 259
- An Analysis of the Die Testing Process Using Taguchi Techniques and Circuit DiagnosticsRobert Trahan, Rex Kiang. 260-269
- Using Tester Repeatability to Improve YieldsRobert James Montoya. 270-274
- Successful Implementation of SPC in Semiconductor Final TestSarkis Ourfalian. 275-282
- Parity-Scan Design to Reduce the Cost of Test ApplicationHideo Fujiwara, Akihiro Yamamoto. 283-292
- Optimal Sequencing of Scan RegistersSridhar Narayanan, Charles Njinda, Melvin A. Breuer. 293-302
- A Graph Theoretic Approach to Partial Scan Design by K-Cycle EliminationSungju Park, Sheldon B. Akers. 303-311
- Test Generation and Concurrent Error Detection in Current-Mode A/D ConvertersShoba Krishnan, Sondes Sahli, Chin-Long Wey. 312-320
- AC Dynamic Testing of 20Bit Sigma-Delta Over-Sampling D/A Converter on a Mixed Signal Test SystemMasao Sugai, Takayuki Nakatani. 321-327
- Memory Interconnection Test at Board LevelFrans de Jong, Adriaan J. de Lind van Wijngaarden. 328-337
- Interconnect and Delay Testing with a 4800-Pin Board TesterShuichi Kameyama, Hideyuki Ohara, Chihiro Endo, Naoki Takayama. 338-344
- VECTOR (Virtual Edge Connector Test): A Strategy to Increase TPS Fault Coverage Without Adding Test VectorsGaspare Pantano, Dave Rolince. 345-351
- Testing Errors: Data and Calculations in an IC Manufacturing ProcessRichard H. Williams, R. Glenn Wagner, Charles F. Hawkins. 352-361
- Position of Component Testing in Total Quality Management (TQM)Babur Mustafa Pulat, Lauren M. Streb. 362-366
- Board Test DFT Model for Computer ProductsMick Tegethoff, T. E. Figal, S. W. Hird. 367-371
- On the Design of Self-Checking Boundary Scannable BoardsMarcelo Lubaszewski, Bernard Courtois. 372-381
- An ATPG Driver Selection Algorithm for Interconnect Test with Boundary ScanWei-Cheng Her, Lin-Ming Jin, Yacoub M. El-Ziq. 382-388
- Automatic Pattern Generation for Diagnosis of Wiring Interconnect FaultsMatthew Melton, Franc Brglez. 389-398
- The Production Implementation of a Linear Error Modeling TechniqueTimothy Daniel Lyons. 399-404
- Simulation of an Integrated Design and Test Environment for Mixed-Signal Integrated CircuitsStephen C. Bateman, William H. Kao. 405-414
- A Steady-State Response Test Generation for Mixed-Signal Integrated CircuitsAlaa F. Alani, Gerry Musgrave, Anthony P. Ambler. 415-421
- High Performance Monolithic Verniers for VLSI Automatic Test EquipmentR. Warren Necoechea. 422-430
- Timing-Per-Pin Flexibility at Shared-Resource CostGary Fehr. 431-438
- TGEN: Flexible Timing Generator ArchitectureTimothy Alton. 439-443
- Economic Impact of Type I Test Errors at System and Board LevelsChristopher L. Henderson, Richard H. Williams, Charles F. Hawkins. 444-452
- EDIF Test - The Upcoming Standard for Test Data TransfersMichael G. Wahl, Carol Pyron. 453-458
- Using EDIF for Transfer of Test Data: Practical ExperienceBas Verhelst, Richard Morren, Keith Baker. 459-465
- Analysis of Steady State Detection of Resistive Bridging Faults in BiCMOS Digital ICsMichele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò. 466-475
- Transistor Fault Coverage for Self-Testing CMOS CheckersPeter Lidén, Peter Dahlgren, Jan Torin. 476-485
- Parametric Bridging Fault Characterization for the Fault Simulation of Library-Based ICsMarcello Dalpasso, Michele Favalli, Piero Olivo, Bruno Riccò. 486-495
- BIST Techniques for ASIC DesignGordon R. Mc Leod. 496-505
- ScanBIST: A Multi-frequency Scan-based BIST MethodBenoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan. 506-513
- A Fast Testing Method for Sequential Circuits at the State Trasition LevelWei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee. 514-519
- A Suite of Novel Digital ATE Timing Calibration MethodsHerbert Thaler, Lee Holt. 520-529
- Calibration Techniques for a Gigahertz Test SystemDavid C. Keezer, R. J. Wenzel. 530-537
- High Performance Pin Electronics with GaAs, A Contradiction in Terms?Ulrich Schoettmer, Holger Engelhard. 538-545
- System Test: What is it? Why Bother Defining It?Maury A. Smeyne. 546
- System Perspective on Diagnostic TestingWilliam R. Simpson, John W. Sheppard. 547
- System Testing: The Future for All of UsCharles F. Hawkins. 548
- Is Burn-In Burned-Out - Part 2Noel E. Donlin. 549-550
- Software Testing: Opportunity and NightmareAnneliese Amschler Andrews. 551-552
- Software Testing: Theory and PracticeSimeon C. Ntafos. 553
- A Mixed Signal Analog Test Bus FrameworkRichard Hulse. 554
- Design for Test Approaches to Mixed-Signal TestingMadhuri Jarwala. 555
- A Structure for Board-Level Mixed-Signal TestabilityB. R. Wilkins. 556-557
- Amdahl Corporation Board Delay Test SystemBejoy G. Oomman, Prasad Kongara, Chittaranjan Mallipeddi. 558-567
- AC Test Quality: Beyond Transition Fault CoverageYaron Aizenbud, Paul Chang, Moshe Leibowitz, Dave Smith, Bernd Könemann, Vijay S. Iyengar, Barry K. Rosen. 568-577
- Delay Test: The Next Frontier for LSSD Test SystemsBernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams. 578-587
- Robustness Enhancement and Detection Threshold Reduction in ATPG for Gate Delay FaultsWeiwei Mao, Michael D. Ciletti. 588-597
- Transparent BIST for RAMsMichael Nicolaidis. 598-607
- LSSD Compatible and Concurrently Testable RamH. Maeno, K. Nii, S. Sakayanagi, S. Kato. 608-614
- A Testing Technique for ULSI Memory with On-Chip Voltage Down ConverterMasaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikishi, Katsunori Suma, Kazuyasu Fujishima. 615-622
- A Self-Testing and Self-Repairing Structure for Ultra-Large Capacity MemoriesTom Chen, Glen Sunada. 623-631
- Testable Designs of Sequential Circuits Under Highly Observable ConditionXiaoqing Wen, Kozo Kinoshita. 632-641
- Physical DFT for High Coverage of Realistic FaultsM. Saraiva, P. Casimiro, Marcelino B. Santos, José T. de Sousa, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira. 642-651
- High Quality Testing of Embedded RAMs Using Circular Self-Test PathAndrzej Krasniewski, Slawomir Pilarski. 652-661
- Warning: 100 Fault Coverage May Be Misleading!!Miron Abramovici, Prashant S. Parikh. 662-668
- Testing a DSP-Based Mixed-Signal Telecommunications ChipPaul Astrachan, Todd Brooks, Jody Everett, Wai-On Law, Kenneth McIntyre, Chuong Nguyen, Charles Weng. 669-677
- An Open Modular Test Concept for the DSP KISS-16VsJ. Preißner, G.-H. Huaman-Bollo, G. Mahlich, Johannes Schuck, Hans Sahm, P. Weingart, D. Weinsziehr, J. Yeandel, R. Evans. 678-683
- Functional Testing of Current Microprocessors (applied to the Intel i860:::TM:::)A. J. van de Goor, Th. J. W. Verhallen. 684-695
- A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault InjectionMarcus Rimén, Joakim Ohlsson. 696-704
- Skewed-Load Transition Test: Part 1, CalculusJacob Savir. 705-713
- Skewed-Load Transition Test: Part 2, CoverageSrinivas Patil, Jacob Savir. 714-722
- Transition Fault Simulation for Sequential CircuitsKwang-Ting Cheng. 723-731
- HIST: A Methodology for the Automatic Insertion of a Hierarchical Self TestOliver F. Haberl, Thomas Kropf. 732-741
- ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial CircuitsPi-Yu Chung, Ibrahim N. Hajj. 742-751
- Design for Testability Using Architectural DescriptionsVivek Chickermane, Jaushin Lee, Janak H. Patel. 752-761
- All Tests for a Fault Are Not Equally Valuable for Defect DetectionRohit Kapur, Jaehong Park, M. Ray Mercer. 762-769
- Detection of Undetectable Faults Using I::DDQ:: TestingRavi K. Gulati, Weiwei Mao, Deepak K. Goel. 770-777
- A Comparison of Defect Models for Fault Location with I::DDQ:: MeasurementsRobert C. Aitken. 778-787
- A Method of Jitter MeasurementEric Rosenfeld. 788-794
- In-Process Inspection Technique for Active-Matrix LCD PanelsTakashi Kido. 795-799
- Testing Video ProcessorsPaul Kelley. 800-806
- One-Pass Redundancy Identification and RemovalMiron Abramovici, Mahesh A. Iyer. 807-815
- Recursive Learning: An Attractive Alternative to the Decision Tree for Test Genration in Digital CircuitsWolfgang Kunz, Dhiraj K. Pradhan. 816-825
- A Test Generation Methodology for High-Performance Computer Chips and ModulesBernd Könemann, Phil Noto. 826-833
- An Automated Optical On-Wager Probing System for Ultra-High-Speed ICsMitsuru Shinagawa, Tadao Nagatsuma. 834-839
- DRC-based Selection of Optimal Probing Points for Chip-Internal MeasurementsR. Scharf, C. Kuntzsch, Klaus Helmreich, Werner Wolz, Klaus D. Müller-Glaser. 840-847
- IDA: A Tool for Computer-Aided Failure AnalysisAlan C. Noble. 848-853
- Test/Agent: CAD-integrated Automatic Generation of Test ProgramsR. Arnold, M. Chowanetz, Werner Wolz, Klaus D. Müller-Glaser. 854-859
- Automatic Test Program Generation for Mixed Signal ICs via Design to Test LinkWilliam Kao, Jean Xia, Tom Boydston. 860-865
- Improving Total IC Design Quality Using Application Mode TestingR. Mehtani, M. De Jonghe, Richard Morren, Keith Baker. 866-872
- Circuit Design for Built-in Current TestingYukiya Miura, Kozo Kinoshita. 873-881
- Non-Conventional Faults in BiCMOS Digital CircuitsSiyad C. Ma, Edward J. McCluskey. 882-891
- Bridging Defects Resistance Measurements in a CMOS ProcessRosa Rodríguez-Montañés, Joan Figueras, Eric Bruls. 892-899
- Designing for Software Testability Using Automated OraclesJames M. Bieman, Hwei Yin. 900-907
- A Simulation Environment for Early Lifecycle Software Reliability Research and PredictionAnneliese Amschler Andrews, James Keables. 908-916
- Intelligent Fault Localization in SoftwareIlene Burnstein, Nitya Jani, Steve Mannina, Joe Tamsevicius, Michael Goldshteyn, Louis Lendi. 917-926
- Advances in Membrane Probe TechnologyJanuary Kister, Robert L. Franch. 927-935
- Enhanced Probe Card Facilities At-Speed Wafer Probing in Very High Density ApplicationsEswar Subramanian, Randy Nelson. 936-939
- A 3GHz, 144 Point Probe Fixture for Automatic IC Wafer TestingDaniel T. Hamling. 940-947
- CMOS Checkers with Testable Bridging and Transistor Stuck-on FaultsCecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò. 948-957
- Merging Concurrent Checking and Off-line BISTXiaoling Sun, Micaela Serra. 958-967
- An Integrated Built-In Self-Testing and Self-Repair of VLSI/WSI Hexagonal ArraysPinaki Mazumder. 968-977
- An Architecture for a Reconfigurable IEEE 1149.n Master Controller BoardKevin T. Kornegay, Robert W. Brodersen. 978-983
- Applications of the IEEE P1149.5 Module Test and Maintenance BusDavid L. Landis, Chuck Hudson, Patrick F. McHugh. 984-992
- A Framework for Boundary-Scan Based System Test DiagnosisNajmi T. Jarwala, Paul Stiling, Enn Tammaru, Chi W. Yau. 993-998
- Implementing 1149.1 on CMOS MicroprocessorsW. C. Bruce, Michael G. Gallup, Grady Giles, Tom Munns. 999-1006