Iyad Ouaiss - researchr alias

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Viewing Publication 1 - 16 from 16

2020

Toward an Improvement of Engineering Teaming Skills Through an In-House Professionalism CourseMohammad Al-Abbas, Wissam Fawaz, Raymond Ghajar, Chadi Abou-Rjeily, Iyad Ouaiss, Zahi Nakad, George E. Nasr, Samer S. Saab 0001. te, 63(4):273-282, 2020. [doi]

2015

Enhanced Technology Mapping for FPGAs with Exploration of Cell ConfigurationsGrace Zgheib, Iyad Ouaiss. jcsc, 24(3), 2015. [doi]

2011

A Novel Register-Binding Approach to Reduce Spurious Switching Activity in High-Level SynthesisElie Elaaraj, Iyad Ouaiss. jcsc, 20(5):943-973, 2011. [doi]

Priority-Driven Area Optimization in High-Level SynthesisMaria Abi Saad, Iyad Ouaiss. jcsc, 20(6):1131-1163, 2011. [doi]

2010

Deadline-based connection setup in wavelength-routed WDM networksWissam Fawaz, Iyad Ouaiss, Ken Chen, Harry G. Perros. cn, 54(11):1792-1804, 2010. [doi]

A novel pseudorandom noise and band jammer generator using a composite sinusoidal functionSamer S. Saab, Jad G. Hobeika, Iyad Ouaiss. tsp, 58(2):535-543, 2010. [doi]

2005

Optimizing register binding in FPGAs using simulated annealingAnnie Avakian, Iyad Ouaiss. reconfig 2005: [doi]

2004

Register Binding for FPGAs with Embedded MemoryHassan Al Atat, Iyad Ouaiss. fccm 2004: 167-175 [doi]

Storage Allocation for Diverse FPGA Memory SpecificationsDalia Dagher, Iyad Ouaiss. fpl 2004: 606-616 [doi]

2001

Memory Synthesis for FPGA-Based Reconfigurable ComputersAmit Kasat, Iyad Ouaiss, Ranga Vemuri. fpl 2001: 70-80 [doi]

Global memory mapping for FPGA-based reconfigurable systemsIyad Ouaiss, Ranga Vemuri. ipps 2001: 144

Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computersIyad Ouaiss, Ranga Vemuri. date 2001: 650-657 [doi]

2000

Efficient Resource Arbitration in Reconfigurable Computing EnvironmentsIyad Ouaiss, Ranga Vemuri. date 2000: 560-566 [doi]

1999

An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP ApplicationsMeenakshi Kaul, Ranga Vemuri, Sriram Govindarajan, Iyad Ouaiss. dac 1999: 616-622 [doi]

1998

An Effective Design System for Dynamically Reconfigurable ArchitecturesSriram Govindarajan, Iyad Ouaiss, Meenakshi Kaul, Vinoo Srinivasan, Ranga Vemuri. fccm 1998: 312-313 [doi]

An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA ArchitecturesIyad Ouaiss, Sriram Govindarajan, Vinoo Srinivasan, Meenakshi Kaul, Ranga Vemuri. ipps 1998: 31-36

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