Abstract is missing.
- A secure self-reconfiguring architecture based on open-source hardwareJavier Castillo, Pablo Huerta, Victor López, José Ignacio Martínez. [doi]
- An FPGA-based coprocessor for the SPHINX speech recognition system: early experiencesGuillermo Marcus, Juan Arturo Nolazco-Flores. [doi]
- A Handel-C implementation of the back-propagation algorithm on field programmable gate arraysVijay Pandya, Shawki Areibi, Medhat Moussa. [doi]
- VHDL core for 1024-point radix-4 FFT computationJose Alberto Vite-Frias, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno. [doi]
- FPGA-based customizable systolic architecture for image processing applicationsGriselda Saldaña, Miguel Arias-Estrada. [doi]
- An image comparison circuit designMiguel Angel Sánchez Martínez, Adriano De Luca Pennacchia. [doi]
- VANNGen: a flexible CAD tool for hardware implementation of artificial neural networksAndré L. S. Braga, Carlos H. Llanos, Mauricio Ayala-Rincón, Ricardo P. Jacobi. [doi]
- An FPGA-based parallel sorting architecture for the Burrows Wheeler transformJosé Francisco Martínez Trinidad, René Cumplido-Parra, Claudia Feregrino Uribe. [doi]
- A novel FPGA implementation of a welding control using a new bus architectureKimmo Rauma, Julius Luukko, Torsti Härkönen, Ilkka Pajari, Olli Pyrhönen. [doi]
- On the design of an FPGA-based OFDM modulator for IEEE 802.16-2004Joaquín García, René Cumplido-Parra. [doi]
- FPGA implementation of a synchronous and self-timed neuroprocessorJuan José Raygoza-Panduro, Susana Ortega-Cisneros, Eduardo Boemo. [doi]
- FPGA implementation of DSVPWM modulatorOssi Laakkonen, Hannu Sarén, Kimmo Rauma, Olli Pyrhönen. [doi]
- Hardware/software implementation of a discrete cosine transform algorithm using SystemCAlfonso Avila-Ortega, Rolando Santoyo-Rincón, Sergio Omar Martinez-Chapa, Graciano Dieck-Assad. [doi]
- Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipationZied Marrakchi, Hayder Mrabet, Habib Mehrez. [doi]
- An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add methodSabel Mercurio Hernández Rodríguez, Francisco Rodríguez-Henríquez. [doi]
- Hardware signal processing unit for one-dimensional variable-length discrete wavelet transformAlejandro Ordaz-Moreno, René de Jesús Romero-Troncoso, Jose Alberto Vite-Frias. [doi]
- Dynamic voting schemes to enhance evolutionary repair in reconfigurable logic devicesCorey J. Milliord, Carthik A. Sharma, Ronald F. DeMara. [doi]
- FPGA implementation of an efficient multiplier over finite fields GF(2/sup m/)Mario Alberto Garcia Martinez, Rubén Posada-Gómez, Guillermo Morales-Luna, Francisco Rodríguez-Henríquez. [doi]
- Optimizing register binding in FPGAs using simulated annealingAnnie Avakian, Iyad Ouaiss. [doi]
- Platform for intrinsic evolution of analogue neural networksPatrick Rocke, John Maher, Fearghal Morgan. [doi]
- High quality uniform random number generation for massively parallel simulations in FPGADavid B. Thomas, Wayne Luk. [doi]
- On the design of two-level reconfigurable architecturesSebastian Lange, Martin Middendorf. [doi]
- Quartz: a framework for correct and efficient reconfigurable designOliver Pell, Wayne Luk. [doi]
- Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scalingMarco Aurelio Nuño-Maganda, Miguel Arias-Estrada. [doi]
- Design space exploration of coarse-grain reconfigurable DSPsMartin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek. [doi]
- Applied VHDL training methodology, EDA framework and hardware implementation platformFearghal Morgan, Patrick Rocke, Martin O'Halloran. [doi]
- Rapid prototyping of a self-timed ALU with FPGAsSusana Ortega-Cisneros, Juan José Raygoza-Panduro, Juan Suardíaz Muro, Eduardo Boemo. [doi]
- Design and implementation of an embedded microprocessor compatible with IL language in accordance to the norm IEC 61131-3Snaider L. Carrillo, Agenor Z. Polo, Mario P. Esmeral. [doi]