An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method - researchr publication

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Sabel Mercurio Hernández Rodríguez, Francisco Rodríguez-Henríquez. An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method. In 2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005. IEEE Computer Society, 2005. [doi]

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