Sabel Mercurio Hernández Rodríguez, Francisco Rodríguez-Henríquez. An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method. In 2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005. IEEE Computer Society, 2005. [doi]
@inproceedings{RodriguezR05-1,
title = {An FPGA arithmetic logic unit for computing scalar multiplication using the half-and-add method},
author = {Sabel Mercurio Hernández Rodríguez and Francisco Rodríguez-Henríquez},
year = {2005},
doi = {10.1109/RECONFIG.2005.8},
url = {http://doi.ieeecomputersociety.org/10.1109/RECONFIG.2005.8},
researchr = {https://researchr.org/publication/RodriguezR05-1},
cites = {0},
citedby = {0},
booktitle = {2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005},
publisher = {IEEE Computer Society},
isbn = {0-7695-2456-7},
}