VHDL core for 1024-point radix-4 FFT computation

Jose Alberto Vite-Frias, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno. VHDL core for 1024-point radix-4 FFT computation. In 2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005. IEEE Computer Society, 2005. [doi]

Abstract

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