Jose Alberto Vite-Frias, René de Jesús Romero-Troncoso, Alejandro Ordaz-Moreno. VHDL core for 1024-point radix-4 FFT computation. In 2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005. IEEE Computer Society, 2005. [doi]
@inproceedings{Vite-FriasRO05,
title = {VHDL core for 1024-point radix-4 FFT computation},
author = {Jose Alberto Vite-Frias and René de Jesús Romero-Troncoso and Alejandro Ordaz-Moreno},
year = {2005},
doi = {10.1109/RECONFIG.2005.36},
url = {http://doi.ieeecomputersociety.org/10.1109/RECONFIG.2005.36},
researchr = {https://researchr.org/publication/Vite-FriasRO05},
cites = {0},
citedby = {0},
booktitle = {2005 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2005, Puebla City, Mexico, September 28-30, 2005},
publisher = {IEEE Computer Society},
isbn = {0-7695-2456-7},
}