Table of Contents

• A powerful global router: based on Steiner min-max treesCharles Chiang, Majid Sarrafzadeh, Chak-Kuen Wong. 2-5 [doi]
• Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning treeJan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong. 6-9 [doi]
• A minimum separation algorithm for river routing with bounded number of jogsAndranik Mirzaian. 10-13 [doi]
• Module assignment and interconnect sharing in register-transfer synthesis of pipelined data pathsNohbyung Park, Fadi J. Kurdahi. 16-19 [doi]
• A new integer linear programming formulation for the scheduling problem in data path synthesisJiahn-Humg Lee, Yu-Chin Hsu, Youn-Long Lin. 20-23 [doi]
• Scheduling and hardware sharing in pipelined data pathsKi-Soo Hwang, Albert E. Casavant, Ching-Tang Chang, Manuel A. d'Abreu. 24-27 [doi]
• Automating the diagnosis and the rectification of design errors with PRIAMJean Christophe Madre, Olivier Coudert, Jean-Paul Billon. 30-33 [doi]
• Accurate logic simulation in the presence of unknownsSusheel J. Chandra, Janak H. Patel. 34-37 [doi]
• Restricted symbolic evaluation is fast and usefulJ. Lawrence Carter, Barry K. Rosen, Gordon L. Smith, Vijay Pitchumani. 38-41 [doi]
• CRACKER: a general area router based on stepwise reshapingSabih H. Gerez, Otto E. Herrmann. 44-47 [doi]
• AGAR: a single-layer router for gate array cell generationMark A. Mostow. 48-51 [doi]
• A new approach to sea-of-gates global routingTai-Ming Parng, Ren-Song Tsay. 52-55 [doi]
• Manual rescheduling and incremental repair of register-level datapathsDavid W. Knapp. 58-61 [doi]
• A resource sharing and control synthesis method for conditional branchesKazutoshi Wakabayashi, Takeshi Yoshimura. 62-65 [doi]
• A logic synthesis system for VHDL design descriptionsThomas E. Dillinger, Kathy M. McCarthy, Thomas A. Mosher, Dale R. Neumann, Randall A. Schmidt. 66-69 [doi]
• A timing model for static CMOS gatesHau-Yung Chen, Santanu Dutta. 72-75 [doi]
• An accurate timing model for fault simulation in MOS circuitsSungho Kim, Prithviraj Banerjee. 76-79 [doi]
• Event-EMU: an event driven timing simulator for MOS VLSI circuitsBryan D. Ackland, Robert A. Clark. 80-83 [doi]
• Automatic mixed-mode timing simulationDavid Overhauser, Ibrahim N. Hajj, Yi-Fan Hsu. 84-87 [doi]
• Global refinement for building block layoutYing-Meng Li, PuShan Tang. 90-93 [doi]
• Timing driven placementMalgorzata Marek-Sadowska, Shen Lin. 94-97 [doi]
• Combining partitioning and global routing in sea-of-cells designBernhard Korte, Hans Jürgen Prömel, Angelika Steger. 98-101 [doi]
• Layout methods for digital optical computingMiles Murdocca. 102-105 [doi]
• Definition and assignment of complex data-paths suited for high throughput applicationsStefaan Note, Francky Catthoor, Jef L. van Meerbergen, Hugo De Man. 108-111 [doi]
• Tree-height minimization in pipelined architecturesRichard I. Hartley, Albert E. Casavant. 112-115 [doi]
• Synthesis of address generatorsDouglas M. Grant, Peter B. Denyer, I. Finlay. 116-119 [doi]
• Timing models in VAL/VHDLLarry M. Augustin. 122-125 [doi]
• On the computation of the ranges of detected delay fault sizesAnkan K. Pramanick, Sudhakar M. Reddy. 126-129 [doi]
• A bounded delay race modelCarl-Johan H. Seger. 130-133 [doi]
• Two-dimensional compaction for placement refinementXiao-Ming Xiong. 136-139 [doi]
• A custom cell generation system for double-metal CMOS technologyP. Gee, Ibrahim N. Hajj, Sung-Mo Kang. 140-143 [doi]
• An O(n log n) algorithm for 1-D tile compactionRichard Anderson, Simon Kahan, Martine D. F. Schlag. 144-147 [doi]
• An efficient algorithm for layout compaction problem with symmetry constraintsR. Okuda, Takashi Sato, Hidetoshi Onodera, K. Tamariu. 148-151 [doi]
• Layout-driven test generationPhil Nigh, Wojciech Maly. 154-157 [doi]
• Optimal granularity of test generation in a distributed systemHideo Fujiwara, Tomoo Inoue. 158-161 [doi]
• The critical path for multiple faultsSamy Makar, Edward J. McCluskey. 162-165 [doi]
• High performance test generation for accurate defect models in CMOS gate array technologyHector R. Sucar, Susheel J. Chandra, David J. Wharton. 166-169 [doi]
• Uninterpreted modeling using the VHSIC hardware description language (VHDL)F. T. Hady, James H. Aylor, Ronald D. Williams, Ronald Waxman. 172-175 [doi]
• Mixed-mode simulation of compiled VHDL programsRamón D. Acosta, Steven P. Smith, J. Larson. 176-179 [doi]
• Switch-level VHDL descriptionsAlec G. Stanculescu, Andy S. Tsay, Alex N. D. Zamfirescu, D. L. Perry. 180-183 [doi]
• VHDL modeling for analog-digital hardware designs (VHSIS hardware description language)Balsha R. Stanisic, Mark W. Brown. 184-187 [doi]
• An efficient method for parametric yield optimization of MOS integrated circuitsTat-Kwan Yu, Sung-Mo Kang, Jerome Sacks, William J. Welch. 190-193 [doi]
• A new methodology for the design centering of IC fabrication processesK. K. Low, Stephen W. Director. 194-197 [doi]
• Statistical bipolar circuit design using MSTATNicolas Salamina, Mark R. Rencher. 198-201 [doi]
• Computation of bus current variance for reliability estimation of VLSI circuitsFarid N. Najm, Ibrahim N. Hajj, Ping Yang. 202-205 [doi]
• Boolean minimization and algebraic factorization procedures for fully testable sequential machinesSrinivas Devadas, Kurt Keutzer. 208-211 [doi]
• State assignment for initializable synthesis (gate level analysis)Kwang-Ting Cheng, Vishwani D. Agrawal. 212-215 [doi]
• Optimum and heuristic algorithms for finite state machine decomposition and partitioningPranav Ashar, Srinivas Devadas, A. Richard Newton. 216-219 [doi]
• State assignment for multilevel logic using dynamic literal estimationMichael Bolotski, Daniel Camporese, Rod Barman. 220-223 [doi]
• An approach for the yield enhancement of programmable gate arraysVijay P. Kumar, Anton T. Dahbura, Fred Fischer, Patrick Juola. 226-229 [doi]
• A novel reconfiguration scheme for 2-D processor arraysPhill K. Rhee, Jung Hwan Kim, H. Y. Youn. 230-233 [doi]
• Fault detection and location in reconfigurable VLSI arraysKuochen Wang, Sy-Yen Kuo. 234-237 [doi]
• Optimal wafer probe testing and diagnosis of k-out-of-n structuresMing-Feng Chang, Weiping Shi, W. Kent Fuchs. 238-241 [doi]
• A table look-up model using a 3-D isoparametric shape function with improved convergencyDae-Hyung Cho, Tae-Han Kim, Jeong-Taek Kong. 244-247 [doi]
• Piecewise approximate circuit simulationChandramouli Visweswariah, Ronald A. Rohrer. 248-251 [doi]
• SPECS simulation validation with efficient transient sensitivity computationTuyen V. Nguyen, Peter Feldmann, Stephen W. Director, Ronald A. Rohrer. 252-255 [doi]
• Thermal analysis in SPICERao Prakash Pokala, Dileep A. Divekar. 256-259 [doi]
• Translating concurrent programs into delay-insensitive circuitsErik Brunvand, Robert F. Sproull. 262-265 [doi]
• Practicality of state-machine verification of speed-independent circuitsSteven M. Nowick, David L. Dill. 266-269 [doi]
• Inserting active delay elements to achieve wave pipeliningDerek C. Wong, Giovanni De Micheli, Michael J. Flynn. 270-273 [doi]
• A data model and architecture for VLSI/CAD databasesAnoop Singhal, Nishit P. Parikh, Debaprosad Dutt, Chi-Yuan Lo. 276-279 [doi]
• SLIP: a software environment for system level interactive partitioningMark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton. 280-283 [doi]
• A data management interface as part of the framework of an integrated VLSI-design systemErnst Siepmann. 284-287 [doi]
• DEC's engineering to manufacturing BRIDGE system based on the D-BUS architectureR. J. Bonneau. 288-291 [doi]
• Optimal layout via Boolean satisfiabilitySrinivas Devadas. 294-297 [doi]
• Towards efficient hierarchical designs by ratio cut partitioningYen-Chuen A. Wei, Chung-Kuan Cheng. 298-301 [doi]
• Pin assignment with global routingJason Cong. 302-305 [doi]
• On optimal extraction of combinational logic and don't care sets from hardware description languagesGlenn Colón-Bonet, Eric M. Schwarz, D. G. Bostick, Gary D. Hachtel, Michael R. Lightner. 308-311 [doi]
• PLA decomposition with generalized decodersSeiyang Yang, Maciej J. Ciesielski. 312-315 [doi]
• An exact minimizer for Boolean relationsRobert K. Brayton, Fabio Somenzi. 316-319 [doi]
• WireLisp: combining graphics and procedures in a circuit specification languageCarl Ebeling, Zhanbing Wu. 322-325 [doi]
• Fast incremental netlist compilation of hierarchical schematicsLarry G. Jones. 326-329 [doi]
• Structure optimization in logic schematic generationTsung D. Lee, Lawrence P. McNamee. 330-333 [doi]
• A new approach to optimal cell synthesisJan Madsen. 336-339 [doi]
• CLEO: a CMOS layout generatorAntun Domic, Samuel Levitin, Nathan Phillips, Channeary Thai, Thomas R. Shiple, Dilip Bhavsar, Clint Bissel. 340-343 [doi]
• An optimal transistor-chaining algorithm for CMOS cell layoutChi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu. 344-347 [doi]
• Fast test generation for sequential circuitsTodd P. Kelsey, Kewal K. Saluja. 345-347 [doi]
• CETUS-a versatile custom cell synthesizerP. K. Sun. 348-351 [doi]
• Design of sequential machines for efficient test generationKwang-Ting Cheng, Vishwani D. Agrawal. 358-361 [doi]
• Test generation for highly sequential circuitsAbhijit Ghosh, Srinivas Devadas, A. Richard Newton. 362-365 [doi]
• FACT-a testability analysis methodologyThirumalai Sridhar. 366-369 [doi]
• Analogue circuit optimization in a graphical environmentP. J. Rankin, J. M. Siemensma. 372-375 [doi]
• A manufacturing-oriented environment for synthesis of fabrication processesJohn S. Wenstrand, Hiroshi Iwai, Robert W. Dutton. 376-379 [doi]
• Yoda: a framework for the conceptual design VLSI systemsAllen M. Dewey, Stephen W. Director. 380-383 [doi]
• The EVE VLSI information management environmentHamideh Afsarmanesh, Esther Brotoatmodjo, Kwang June Byeon, Alice C. Parker. 384-387 [doi]
• Interconnection length estimation for optimized standard cell layoutsMassoud Pedram, Bryan Preas. 390-393 [doi]
• Early matching of system requirements and package capabilitiesDavid P. LaPotin, Y. H. Chen. 394-397 [doi]
• A clock distribution scheme for nonsymmetric VLSI circuitsParameswaran Ramanathan, Kang G. Shin. 398-401 [doi]
• A Newton waveform relaxation algorithm for circuit simulationDonald J. Erdman, Donald J. Rose. 404-407 [doi]
• PGS and PLUCGS-two new matrix solution techniques for general circuit simulationRichard Burch, Kartikeya Mayaram, Jue-Hsien Chern, Ping Yang, Paul F. Cox. 408-411 [doi]
• Waveform relaxation for transient simulation of two-dimensional MOS devicesMark W. Reichelt, Jacob K. White, Jonathan Allen. 412-415 [doi]
• Synthesis of delay fault testable combinational logicKaushik Roy, Jacob A. Abraham, Kaushik De, Stephen L. Lusky. 418-421 [doi]
• On properties of algebraic transformation and the multifault testability of multilevel logicGary D. Hachtel, Reily M. Jacoby, Kurt Keutzer, Christopher R. Morrison. 422-425 [doi]
• Consistency and observability invariance in multi-level logic synthesisPatrick C. McGeer, Robert K. Brayton. 426-429 [doi]
• An efficient channel routing algorithm for defective arraysHee Yong Youn, Adit D. Singh. 432-435 [doi]
• Routing using a pyramid data structureYoun-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai. 436-439 [doi]
• HAM-a hardware accelerator for multi-layer wire routingRaja Venkateswaran, Pinaki Mazumder. 440-443 [doi]
• FDT-a design tool for switched capacitor filtersSattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild. 446-449 [doi]
• LADIES: an automatic layout system for analog LSI'sMasato Mogaki, Naoki Kato, Youko Chikami, Naoyuki Yamada, Yasuhiro Kobayashi. 450-453 [doi]
• Functional comparison of logic designs for VLSI circuitsC. Leonard Berman, Louise Trevillyan. 456-459 [doi]
• Specification and verification of VLSI systemsAsher Wilk, Amir Pnueli. 460-463 [doi]
• Dynamic redundancy identification in automatic test generationMiron Abramovici, David T. Miller, Rabindra K. Roy. 466-469 [doi]
• FANHAT: fanout oriented hierarchical automatic test generation systemHyoung B. Min, William A. Rogers, Hwei-Tsu Ann Luh. 470-473 [doi]
• Exact critical path tracing fault simulation on massively parallel processor AAP2Y. Kitamura. 474-477 [doi]
• High-speed compiled-code simulation of transition faultsManfred Geilert. 478-481 [doi]
• An algorithm for hierarchical floorplan designD. F. Wong, Khe-Sing The. 484-487 [doi]
• Constrained floorplan design for flexible blocksSai-keung Dong, Jason Cong, C. L. Liu. 488-491 [doi]
• Multi-terrain partitioning and floor-planning for data-path chip (microprocessor) layoutWing K. Luk, Alvar A. Dean, John W. Mathews. 492-495 [doi]
• Hierarchical compiled event-driven logic simulationDavid M. Lewis. 498-501 [doi]
• A model for comparing synchronization strategies for parallel logic-level simulationMary L. Bailey, Lawrence Snyder. 502-505 [doi]
• Portable parallel logic and fault simulationRobert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham. 506-509 [doi]
• Modeling the driving-point characteristic of resistive interconnect for accurate delay estimationPeter R. O'Brien, Thomas L. Savarino. 512-515 [doi]
• Modeling uncertainty in RC timing analysisCheryl Harkness, Daniel P. Lopresti. 516-519 [doi]
• Critical path issue in VLSI designHabib Youssef, Eugene Shragowitz, Lionel Bening. 520-523 [doi]
• PACE2: an improved parallel VLSI extractor with parameter extractionKrishna P. Belkhale, Prithviraj Banerjee. 526-529 [doi]
• C3DSTAR: a 3D wiring capacitance calculatorJames Janak, David D. Ling, Hao Ming Huang. 530-533 [doi]
• The Stickizer: a layout to symbolic converterJean-Claude Dufourd. 534-537 [doi]
• A layout defect-sensitivity extractorJosé Pineda de Gyvez, Jochen A. G. Jess. 538-541 [doi]
• Fast two-level logic minimizers for multi-level logic synthesisHamid Savoj, Abdul A. Malik, Robert K. Brayton. 544-547 [doi]
• New ATPG techniques for logic optimizationReily M. Jacoby, P. Moceyunas, Hyunwoo Cho, Gary D. Hachtel. 548-551 [doi]
• SYLON-DREAM: a multi-level network synthesizerKuang-Chien Chen, Saburo Muroga. 552-555 [doi]
• Multi-level logic optimization using binary decision diagramsYusuke Matsunaga, Masahiro Fujita. 556-559 [doi]
• TIGER: testability insertion guidance expert systemMagdy S. Abadir. 562-565 [doi]
• Fault detection in a testable PLA with low overhead for production testingYi-Nan Shen, Fabrizio Lombardi. 566-569 [doi]
• Arithmetic and galois checksumsNirmal R. Saxena, Edward J. McCluskey. 570-573 [doi]
• A diagnosis method using pseudo-random vectors without intermediate signaturesRobert C. Aitken, Vinod K. Agarwal. 574-577 [doi]