Eugene Shragowitz - researchr alias

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Viewing Publication 1 - 29 from 29

2006

Iterative-Constructive Standard Cell Placer for High Speed and Low PowerSungjae Kim, Eugene Shragowitz. iccd 2006: 350-355 [doi]

2003

Transaction-based waveform analysis for IP selectionJian Liu, Eugene Shragowitz. aspdac 2003: 104-107 [doi]

Iterative Converging Algorithms for Computing Bounds on Durations of Activities in Pert and Pert-Like ModelsEugene Shragowitz, Habib Youssef, Bing Lu. jco, 7(1):5-22, 2003. [doi]

2002

Net criticality revisited: an effective method to improve timing in physical designH. Chang, Eugene Shragowitz, Jian Liu, Habib Youssef, Bing Lu, Suphachai Sutanthavibul. ispd 2002: 155-160 [doi]

A polynomial time approximation scheme for rectilinear Steiner minimum tree construction in the presence of obstaclesJian Liu, Ying Zhao 0008, Eugene Shragowitz, George Karypis. icecsys 2002: 781-784 [doi]

2001

Combining Hierarchical Filtering, Fuzzy Logic, and Simulation with Software Agents for IP (Intellectual Property) Selection in Electronic DesignJian Liu, Eugene Shragowitz, Wei-Tek Tsai. ijait, 10(3):303-323, 2001.

Wire segmenting for buffer insertion based on RSTP-MSPBing Lu, Jun Gu, Xiao-Dong Hu, Eugene Shragowitz. TCS, 262(1):257-267, 2001. [doi]

1998

Application of fuzzy logic in computer-aided VLSI designEugene Shragowitz, Jun-Yong Lee, Eric Q. Kang. tfs, 6(1):163-172, 1998. [doi]

1995

Generic fuzzy logic CAD development toolEric Q. Kang, Eugene Shragowitz. aspdac 1995: [doi]

Performance Driven Technology Mapper for FPGAs with Complex Logic Block StructuresJun-Yong Lee, Eugene Shragowitz. iscas 1995: 1219-1222

Technology mapping for FPGAs with complex block architectures by fuzzy logic techniquesJung-Yong Lee, Eugene Shragowitz. aspdac 1995: [doi]

1994

Fuzzy logic approach to VLSI placementEric Q. Kang, Rung-Bin Lin, Eugene Shragowitz. tvlsi, 2(4):489-501, 1994. [doi]

1993

Bounds on net lengths for high-speed PCBJaebum Lee, Eugene Shragowitz, David J. Poli. iccad 1993: 73-76 [doi]

An adaptive timing-driven placement for high performance VLSIsSuphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin. tcad, 12(10):1488-1498, 1993. [doi]

1992

Fuzzy Logic Approach to Placement ProblemRung-Bin Lin, Eugene Shragowitz. dac 1992: 153-158 [doi]

Prelayout timing analysis of cell-based VLSI designsHabib Youssef, Eugene Shragowitz, Suphachai Sutanthavibul. cad, 24(7):367-379, 1992. [doi]

1991

An analytical approach to floorplan design and optimizationSuphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen. tcad, 10(6):761-769, 1991. [doi]

Dynamic Prediction of Critical Paths and Nets for Constructive Timing-Driven PlacementSuphachai Sutanthavibul, Eugene Shragowitz. dac 1991: 632-635 [doi]

Bounds on Net Delays for Physical Design of Fast CircuitsHabib Youssef, Rung-Bin Lin, Eugene Shragowitz. vlsi 1992: 111-118

1990

An Analytical Approach to Floorplan Design and OptimizationSuphachai Sutanthavibul, Eugene Shragowitz, J. Ben Rosen. dac 1990: 187-192 [doi]

An Adaptive Timing-Driven Layout for High Speed VLSISuphachai Sutanthavibul, Eugene Shragowitz. dac 1990: 90-95 [doi]

Timing Constraints for Correct PerformanceHabib Youssef, Eugene Shragowitz. iccad 1990: 24-27

1989

Critical path issue in VLSI designHabib Youssef, Eugene Shragowitz, Lionel Bening. iccad 1989: 520-523 [doi]

1988

A Hypercube Algorithm for the 0/1 Knapsack ProblemJong Lee, Eugene Shragowitz, Sartaj Sahni. jpdc, 5(4):438-456, 1988.

1987

A Hypecube Algorithm for the 0/1 Knapsack ProblemJong Lee, Sartaj Sahni, Eugene Shragowitz. icpp 1987: 699-706

A global router based on a multicommodity flow modelEugene Shragowitz, S. Keel. integration, 5(1):3-16, 1987. [doi]

1986

Automated layout synthesis in the YASC silicon compilerDavid E. Krekelberg, Eugene Shragowitz, Gerald E. Sobelman, Li-Shin Lin. dac 1986: 447-453 [doi]

Simulated annealing and combinatorial optimizationSurendra Nahar, Sartaj Sahni, Eugene Shragowitz. dac 1986: 293-299 [doi]

1985

Experiments with simulated annealingSurendra Nahar, Sartaj Sahni, Eugene Shragowitz. dac 1985: 748-752 [doi]

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