Abstract is missing.
- Maximum Current Estimation in CMOS CircuitsHarish Kriplani, Farid N. Najm, Ibrahim N. Hajj. 2-7 [doi]
- Incremental Circuit Simulation Using Waveform RelaxationYun-Cheng Ju, Resve A. Saleh. 8-11 [doi]
- Parallel Waveform Relaxation of Circuits with Global Feedback LoopsT. A. Johnson, Albert E. Ruehli. 12-15 [doi]
- On the Over-Specification Problem in Sequential ATPG AlgorithmsKwang-Ting Cheng, Hi-Keung Tony Ma. 16-21 [doi]
- Freeze!: A New Approach for Testing Sequential CircuitsMiron Abramovici, Krishna B. Rajan, David T. Miller. 22-25 [doi]
- SWiTEST: A Switch Level Test Generation System for CMOS Combinational CircuitsKuen-Jong Lee, Charles Njinda, Melvin A. Breuer. 26-29 [doi]
- Fast Exact and Quasi-Minimal Minimization of Highly Testable Fixed-Polarity AND/XOR Canonical NetworksAndisheh Sarabi, Marek A. Perkowski. 30-35 [doi]
- Implicit and Incremental Computation of Primes and Essential Primes of Boolean FunctionsOlivier Coudert, Jean Christophe Madre. 36-39 [doi]
- Symbolic Prime Generation for Multiple-Valued FunctionsBill Lin, Olivier Coudert, Jean Christophe Madre. 40-44 [doi]
- FPGA Design Principles (A Tutorial)Dwight D. Hill, Ewald Detjens. 45-46 [doi]
- Net Partitions Yield Better Module PartitionsJason Cong, Lars W. Hagen, Andrew B. Kahng. 47-52 [doi]
- Performance-Driven System Partitioning on Multi-Chip ModulesMinshine Shih, Ernest S. Kuh, Ren-Song Tsay. 53-56 [doi]
- A Wire Length Estimation Technique Utilizing Neighborhood Density EquationsTakeo Hamada, Chung-Kuan Cheng, Paul M. Chau. 57-61 [doi]
- A Graph Theoretic Technique to Speed up Floorplan Area OptimizationTing-Chi Wang, D. F. Wong. 62-68 [doi]
- Canonical Embedding of Rectangular Duals with Applications to VLSI FloorplanningSusmita Sur-Kolay, Bhargab B. Bhattacharya. 69-74 [doi]
- Simulating Lossy Interconnect with High Frequency Nonidealities in Linear TimeJaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson. 75-80 [doi]
- Transient Simulation of Lossy InterconnectShen Lin, Ernest S. Kuh. 81-86 [doi]
- AWESpice: A General Tool for the Accurate and Efficient Simulation of Interconnect ProblemsVivek Raghavan, J. Eric Bracken, Ronald A. Rohrer. 87-92 [doi]
- A Boundary-Element Approach to Transient simulation of Three-Dimensional Integrated Circuit InterconnectDavid D. Ling, S. Kim, J. White. 93-98 [doi]
- Move Frame Scheduling and Mixed Scheduling-Allocation for the Automated Synthesis of Digital SystemsMehrdad Nourani, Christos A. Papachristou. 99-105 [doi]
- Representing Conditional Branches for High-Level Synthesis ApplicationsMinjoong Rim, Rajiv Jain. 106-111 [doi]
- Optimal Scheduling and Allocation of Embedded VLSI ChipsCatherine H. Gebotys. 116-119 [doi]
- Optimal Allocation and Binding in High-Level SynthesisMinjoong Rim, Rajiv Jain, Renato De Leone. 120-123 [doi]
- Time Constrained Allocation and Assignment Techniques for High Throughput Signal ProcessingWerner Geurts, Francky Catthoor, Hugo De Man. 124-127 [doi]
- An Engineering Environment for Hardware/Software Co-SimulationDavid Becker, Raj K. Singh, Stephen G. Tell. 129-134 [doi]
- High Level Synthesis of Pipelined Instruction Set Processors and Back-End CompilersIng-Jer Huang, Alvin M. Despain. 135-140 [doi]
- APT: An Area-Performance-Testability Driven Placement AlgorithmSungho Kim, Prithviraj Banerjee, Vivek Chickermane, Janak H. Patel. 141-146 [doi]
- A Performance Driven Macro-Cell Placement AlgorithmTong Gao, Pravin M. Vaidya, C. L. Liu. 147-152 [doi]
- Fuzzy Logic Approach to Placement ProblemRung-Bin Lin, Eugene Shragowitz. 153-158 [doi]
- Delay Fault Test Generation for Scan/Hold Circuits Using Boolean ExpressionsDebashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal. 159-164 [doi]
- Delay Fault Models and Test Generation for Random Logic Sequential CircuitsTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell. 165-172 [doi]
- Equivalence of Robust Delay-Fault and Single Stuck-Fault Test GenerationAlexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 173-176 [doi]
- At-Speed Delay Testing of Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 177-181 [doi]
- The Princeton University Behavioral Synthesis SystemWayne Wolf, Andrés Takach, Chun-Yao Huang, Richard Manno, Ephrem Wu. 182-187 [doi]
- High-Level Synthesis from VHDL with Exact Timing ConstraintsA. Stoll, Peter Duzy. 188-193 [doi]
- Synthesis from Production-Based SpecificationsAndrew Seawright, Forrest Brewer. 194-199 [doi]
- Generalized Moment-Matching Methods for Transient Analysis of Interconnect NetworksEli Chiprout, Michel S. Nakhla. 201-206 [doi]
- On the Stability of Moment-Matching Approximations in Asymptotic Waveform EvaluationDemos F. Anastasakis, Nanda Gopal, Seok-Yoon Kim, Lawrence T. Pillage. 207-212 [doi]
- AWEsymbolic: Compiled Analysis of Linear(ized) Circuits using Asymptotic Waveform EvaluationJohn Y. Lee, Ronald A. Rohrer. 213-218 [doi]
- Specification Partitioning for System DesignFrank Vahid, Daniel Gajski. 219-224 [doi]
- Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software ComponentsRajesh K. Gupta, Claudionor José Nunes Coelho Jr., Giovanni De Micheli. 225-230 [doi]
- High-Level Synthesis with Pin Constraints for Multiple-Chip DesignsYung-Hua Hung, Alice C. Parker. 231-234 [doi]
- Partitioning by Regularity ExtractionD. Sreenivasa Rao, Fadi J. Kurdahi. 235-238 [doi]
- A Path-Oriented Approach for Reducing Hazards in Asynchronous DesignsMeng-Lin Yu, P. A. Subrahmanyam. 239-244 [doi]
- Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm RevisitedAlexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 245-248 [doi]
- Circuit Enhancement by Eliminating Long False PathsHsi-Chuan Chen, David Hung-Chang Du, Siu-Wing Cheng. 249-252 [doi]
- Estimation of Average Switching Activity in Combinational and Sequential CircuitsAbhijit Ghosh, Srinivas Devadas, Kurt Keutzer, Jacob White. 253-259 [doi]
- Why Data Models Will Become the Fastest Growing Segment of the EDA Market (Panel Abstract)William Lattin. 260 [doi]
- Hierarchical Test Generation under Intensive Global Functional ConstraintsJaushin Lee, Janak H. Patel. 261-266 [doi]
- A Methodology to Reduce the Computational Cost of Behavioral Test Pattern GenerationJean François Santucci, Gérard Dray, Norbert Giambiasi, Marc Boumédine. 267-272 [doi]
- Automatic Test Knowledge Extraction from VHDL (ATKET)Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir. 273-278 [doi]
- Functional Synthesis Using Area and Delay OptimizationElke A. Rundensteiner, Daniel Gajski. 291-296 [doi]
- Hierarchical Pitchmatching Compaction Using Minimum DesignCyrus Bamji, Ravi Varadarajan. 311-317 [doi]
- Process Independent Constraint Graph CompactionDavid G. Boyer. 318-322 [doi]
- A New Hierarchical Layout Compactor Using Simplified Graph ModelsWonjong Kim, Joohack Lee, Hyunchul Shin. 323-326 [doi]
- On Efficient Concurrent Fault Simulation for Synchronous Sequential CircuitsDong-Ho Lee, Sudhakar M. Reddy. 327-331 [doi]
- HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential CircuitsHyung Ki Lee, Dong Sam Ha. 336-340 [doi]
- On the Distribution of Fault Coverage and Test length in Random Testing of Combinational CircuitsAmitava Majumdar, Sarma Sastry. 341-346 [doi]
- Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage FaultsSreejit Chakravarty, Minsheng Liu. 353-356 [doi]
- A Novel Approach to Delay-Fault DiagnosisPatrick Girard, Christian Landrault, Serge Pravossoudovitch. 357-360 [doi]
- TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired ConnectionsKevin Chung, Jonathan Rose. 361-367 [doi]
- Area and Delay Mapping for Table-Look-Up Based Field Programmable Gate ArraysPrashant Sawkar, Donald E. Thomas. 368-373 [doi]
- Characterization of Boolean Functions for Rapid Matching in FPGA Technology MappingUlf Schlichtmann, Franc Brglez, Michael Hermann. 374-379 [doi]
- An Improved Synthesis Algorithm for Multiplexor-Based PGA sRajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 380-386 [doi]
- Analyzing Cycle Stealing on Synchronous Circuits with Level-Sensitive LatchesIchiang Lin, John A. Ludwig, Kwok Eng. 393-398 [doi]
- Computing Optimal Clock SchedulesThomas G. Szymanski. 399-404 [doi]
- On the Temporal Equivalence of Sequential CircuitsNarendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 405-409 [doi]
- An Approach to Symbolic Timing VerificationTod Amon, Gaetano Borriello. 410-413 [doi]
- Validating Discrete Event Simulations Using Event Pattern MappingsBenoit A. Gennart, David C. Luckham. 414-419 [doi]
- Two New Techniques for Compiled Multi-Delay Logic SimulationYun Sik Lee, Peter M. Maurer. 420-423 [doi]
- Performance Evaluation of an Event-Driven Logic Simulation MachineFumiyasu Hirose. 428-431 [doi]
- HLSIM - A New Hierarchical Logic Simulator and Netlist ConverterD. A. Zein, O. P. Engel, Gary S. Ditlow. 432-437 [doi]
- Coalgebraic Division for Multilevel Logic SynthesisWen-Jun Hsu, Wen-Zen Shen. 438-442 [doi]
- Efficient Sum-to-One Subsets Algorithm for Logic OptimizationKuang-Chien Chen, Masahiro Fujita. 443-448 [doi]
- Optimization of Primitive Gate Networks Using Multiple Output Two-Level MinimizationAbdul A. Malik. 449-453 [doi]
- Test-Set Preserving Logic TransformationsMichael J. Batek, John P. Hayes. 454-458 [doi]
- Tools to Aid in Wiring Rule Generation for High Speed InterconnectsPaul D. Franzon, Slobodan Simovich, Michael Steer, Mark Basel, Sharad Mehrotra, Tom Mills. 466-471 [doi]
- IPDA: Interconnect Performance Design AssistantNorman H. Chang, Keh-Jeng Chang, John Leo, Ken Lee, Soo-Young Oh. 472-477 [doi]
- On the Circuit Implementation ProblemWing Ning Li, Andrew Lim, Prathima Agrawal, Sartaj Sahni. 478-483 [doi]
- BDDMAP: A Technology Mapper Based on a New Covering AlgorithmDavid S. Kung, Robert F. Damiano, Theresa A. Nix, David J. Geiger. 484-487 [doi]
- LATTIS: An Iterative Speedup Heuristic for Mapped LogicJohn P. Fishburn. 488-491 [doi]
- Why is Today s CAD Inadequate for Designing Tomorrow s Computers (Panel Abstract)Arny Goldfein. 499 [doi]
- Design Process Management for CAD FrameworksMargarida F. Jacome, Stephen W. Director. 500-505 [doi]
- Application-Driven Design Automation for Microprocessor DesignIksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain. 512-517 [doi]
- Power and Ground Network Topology Optimization for Cell Based VLSIsTakashi Mitsuhashi, Ernest S. Kuh. 524-529 [doi]
- FARM: An Efficient Feed-Through Pin Assignment AlgorithmXianlong Hong, Jin Huang, Chung-Kuan Cheng, Ernest S. Kuh. 530-535 [doi]
- The Role of Long and Short Paths in Circuit Performance OptimizationSiu-Wing Cheng, Hsi-Chuan Chen, David Hung-Chang Du, Andrew Lim. 543-548 [doi]
- Certified Timing Verification and the Transition Delay of a Logic CircuitSrinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang. 549-555 [doi]
- Recurrence Equations and the Optimization of Synchronous Logic CircuitsMaurizio Damiani, Giovanni De Micheli. 556-561 [doi]
- Finite State Machine Synthesis with Fault Tolerant Test FunctionSrimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal. 562-567 [doi]
- Solving the State Assignment Problem for Signal Transition GraphsLuciano Lavagno, Cho W. Moon, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 568-572 [doi]
- State Assignment Using Input/Output FunctionsIrith Pomeranz, Kwang-Ting Cheng. 573-577 [doi]
- A New Efficient Approach to Multilayer Channel Routing ProblemSung-Chuan Fang, Wu-Shiung Feng, Shian-Lang Lee. 579-584 [doi]
- A Multi-Layer Channel Router with New Style of Over-the-Cell RoutingTakashi Fujii, Yoko Mima, Tsuneo Matsuda, Takeshi Yoshimura. 585-588 [doi]
- New Models for Four- and Five-Layer Channel RoutingTai-Tsung Ho. 589-593 [doi]
- A Pin Permutation Algorithm for Improving Over-the-Cell Channel RoutingCliff Yungchin Hou, C. Y. Roger Chen. 594-599 [doi]
- Over-the-Cell Channel Routing for High Performance CircuitsSivakumar Natarajan, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh. 600-603 [doi]
- Over-the-Cell Routers for New Cell ModelBo Wu, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh. 604-607 [doi]
- Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical VerificationYung-Te Lai, Sarma Sastry. 608-613 [doi]
- A New Model for Improving symbolic Product Machine TraversalGianpiero Cabodi, Paolo Camurati, Fulvio Corno, Silvano Gai, Paolo Prinetto, Matteo Sonza Reorda. 614-619 [doi]
- Exact Calculation of Synchronization Sequences Based on Binary Decision DiagramsCarl Pixley, Seh-Woong Jeong, Gary D. Hachtel. 620-623 [doi]
- Functional Approaches to Generating Orderings for Efficient Symbolic RepresentationsM. Ray Mercer, Rohit Kapur, Don E. Ross. 624-627 [doi]
- Inductive Verification of Iterative SystemsJune-Kyung Rho, Fabio Somenzi. 628-633 [doi]
- The Automatic Generation of Bus-Interface ModelsYew-Hong Leong, William P. Birmingham. 634-637 [doi]
- Superpipelined Control and Data Path SynthesisUsha Prabhu, Barry M. Pangrle. 638-643 [doi]
- Distributed Design-Space Exploration for High-Level Synthesis SystemsRajiv Dutta, Jayanta Roy, Ranga Vemuri. 644-650 [doi]
- An Efficient algorithm for Microword Length MinimizationRuchir Puri, Jun Gu. 651-656 [doi]
- Control Optimization in High-Level Synthesis Using Behavioral Don t CaresReinaldo A. Bergamaschi, Donald Lobo, Andreas Kuehlmann. 657-661 [doi]
- Transformation-Based High-Level Synthesis of Fault-Tolerant ASICsRamesh Karri, Alex Orailoglu. 662-665 [doi]
- The Electronic Design Interchange Format EDIF: Present and FutureHilary J. Kahn, Richard Goldman. 666-671 [doi]
- Experiments with a Performance Driven Module GeneratorSoohong Kim, Robert Michael Owens, Mary Jane Irwin. 687-690 [doi]
- Plane Parallel a Maze Router and Its Application to FPGAsMikael Palczewski. 691-697 [doi]
- A Mixed-Integer Nonlinear Programming Approach to Analog Circuit SynthesisPrabir C. Maulik, L. Richard Carley, Rob A. Rutenbar. 698-703 [doi]
- An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog CircuitsAbhijit Dharchoudhury, Sung-Mo Kang. 704-709 [doi]
- Multipole-Accelerated 3-D Capacitance Extraction Algorithms for Structures with Conformal DielectricsKeith Nabors, Jacob White. 710-715 [doi]
- The State of EDA Standards (Panel Abstract)John P. Eurich. 716 [doi]