Alvin M. Despain - researchr alias

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Viewing Publication 1 - 68 from 68

2006

Design and evaluation of a hierarchical decoupled architectureWon Woo Ro, Stephen P. Crago, Alvin M. Despain, Jean-Luc Gaudiot. tjs, 38(3):237-259, 2006. [doi]

2003

Position error signal estimation at high sampling rates using data and servo sector measurementsPetros A. Ioannou, Elias B. Kosmatopoulos, Alvin M. Despain. tcst, 11(3):325-334, 2003. [doi]

HiDISC: A Decoupled Architecture for Data-Intensive ApplicationWon Woo Ro, Jean-Luc Gaudiot, Stephen P. Crago, Alvin M. Despain. ipps 2003: 3 [doi]

2002

Position error signal estimation at high sampling rates using data and servo sector measurementsPetros A. loannou, Elias B. Kosmatopoulos, Alvin M. Despain. cdc 2002: 67-72 [doi]

1998

Simulating the Effect of Decoherence and Inaccuracies on a Quantum ComputerKevin M. Obenland, Alvin M. Despain. qcqc 1998: 447-459 [doi]

Low-power state assignment targeting two- and multilevel logic implementationsChi-Ying Tsui, Massoud Pedram, Alvin M. Despain. tcad, 17(12):1281-1291, 1998. [doi]

1997

State assignment based on two-dimensional placement and hypercube mappingShihming Liu, Massoud Pedram, Alvin M. Despain. integration, 24(2):101-118, 1997. [doi]

Design and Simulation of the Aquarius-II MultiprocessorVason P. Srini, Tam M. Nguyen, Darren R. Busing, Michael J. Carlton, Bruce K. Holmer, Georges E. Smine, Alvin M. Despain. jsi, 7(2):151-178, 1997.

1996

Design and Analysis of Hardware for High-Performance PrologBruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Alvin M. Despain. jlp, 29(1-3):107-139, 1996.

Correction to Power Estimation Methods for Sequential Logic Circuits [Correspondence]Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin. tvlsi, 4(4):495, 1996. [doi]

1995

Synthesis of application specific instruction setsIng-Jer Huang, Alvin M. Despain. tcad, 14(6):663-675, 1995. [doi]

A Fast State Assignment Procedure for Large FSMsShihming Liu, Massoud Pedram, Alvin M. Despain. dac 1995: 327-332 [doi]

PLATO P: PLA Timing Optimization by PartitioningShihming Liu, Massoud Pedram, Alvin M. Despain. iscas 1995: 1744-1747

190-MHz CMOS 4-Kbyte Pipelined CachesApoorv Srivastava, Yong-Seon Koh, Barton Sano, Alvin M. Despain. iscas 1995: 1053-1056

Cache designs for energy efficiencyChing-Long Su, Alvin M. Despain. hicss 1995: 306-315 [doi]

Cache design trade-offs for power and performance optimization: a case studyChing-Long Su, Alvin M. Despain. islped 1995: 63-68 [doi]

Power estimation methods for sequential logic circuitsChi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin. tvlsi, 3(3):404-416, 1995. [doi]

1994

Synthesis of Instruction Sets for Pipelined MicroprocessorsIng-Jer Huang, Alvin M. Despain. dac 1994: 5-11 [doi]

Generating instruction sets and microarchitectures from applicationsIng-Jer Huang, Alvin M. Despain. iccad 1994: 391-396 [doi]

Branch with Masked Squashing in Superpipelined ProcessorsChing-Long Su, Alvin M. Despain. isca 1994: 130-140

A Study of Cache Hashing Functions for Symbolic Applications in Micro-Parallel ProcessorsChing-Long Su, Chin-Chi Teng, Alvin M. Despain. icpads 1994: 530-537

Minimizing branch misprediction penalties for superpipelined processorsChing-Long Su, Alvin M. Despain. euromicro 1994: 138-142 [doi]

Hardware-software co-designing benchmark-driven superpipelined instruction set processorsChing-Long Su, Alvin M. Despain. compsac 1994: [doi]

Lower Power Architecture Design and Compilation Techniques for High-Performance ProcessorsChing-Long Su, Chi-Ying Tsui, Alvin M. Despain. compcon 1994: 489-498

Saving Power in the Control Path of Embedded ProcessorsChing-Long Su, Chi-Ying Tsui, Alvin M. Despain. dt, 11(4):24-30, 1994. [doi]

Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMsChi-Ying Tsui, Massoud Pedram, Alvin M. Despain. dac 1994: 18-23 [doi]

Low power state assignment targeting two-and multi-level logic implementationsChi-Ying Tsui, Massoud Pedram, Chih-Ang Chen, Alvin M. Despain. iccad 1994: 82-87 [doi]

Power efficient technology decomposition and mapping under an extended power consumption modelChi-Ying Tsui, Massoud Pedram, Alvin M. Despain. tcad, 13(9):1110-1122, 1994. [doi]

1993

Hardware/software resolution of pipeline hazards in pipeline synthesis of instruction set processorsIng-Jer Huang, Alvin M. Despain. iccad 1993: 594-599 [doi]

An extended classification of inter-instruction dependency and its application in automatic synthesis of pipelined processorsIng-Jer Huang, Alvin M. Despain. euromicro 1993: 236-246 [doi]

PDAS: Processor design automation systemIksoo Pyo, Alvin M. Despain. eurodac 1993: 144-149 [doi]

The 16-fold way: a microparallel taxonomyBarton Sano, Alvin M. Despain. euromicro 1993: 60-69 [doi]

Prophetic branches: a branch architecture for code compaction and efficient executionApoorv Srivastava, Alvin M. Despain. euromicro 1993: 94-99 [doi]

Efficient estimation of dynamic power consumption under a real delay modelChi-Ying Tsui, Massoud Pedram, Alvin M. Despain. iccad 1993: 224-228 [doi]

Technology Decomposition and Mapping Targeting Low Power DissipationChi-Ying Tsui, Massoud Pedram, Alvin M. Despain. dac 1993: 68-73 [doi]

1992

1991

AI and DesignSaul Amarel, Alvin M. Despain, H. Penny Nii, Louis I. Steinberg, Marty Tenenbaum, Peter M. Will. IJCAI 1991: 563-568

An integrated prolog architecture for symbolic and numeric executionsAlvin M. Despain, Robert Yung. AMAI, 4:107-133, 1991.

Viewing Instruction Set Design as an Optimization ProblemBruce K. Holmer, Alvin M. Despain. micro 1991: 153-162 [doi]

1990

The Aquarius IIU SystemDarren R. Busing, Vason P. Srini, Georges E. Smine, Michael J. Carlton, Alvin M. Despain. saicsit 1990: 38-46

The Performance of Parallel Prolog ProgramsBarry S. Fagin, Alvin M. Despain. TC, 39(12):1434-1445, 1990.

Fast Prolog with an Extended General Purpose ArchitectureBruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Ralph Clarke Haygood, William R. Bush, Alvin M. Despain, Joan M. Pendleton, Tep P. Dobry. isca 1990: 282-291

The Benefits of Global Dataflow Analysis for an Optimizing Prolog CompilerPeter Van Roy, Alvin M. Despain. SLP 1990: 501-515

Scalable Shared-Memory Multiprocessor ArchitecturesShreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, Alvin M. Despain. Computer, 23(6):71-83, 1990.

1988

Prolog at BerkeleyAlvin M. Despain. compcon 1988: 64-67

A two-tier memory architecture for high-performance multiprocessor systemsTam M. Nguyen, Vason P. Srini, Alvin M. Despain. ics 1988: 326-336 [doi]

1987

1986

Multiprocessor Cache Synchronization: Issues, Innovations, EvolutionPhilip Bitar, Alvin M. Despain. isca 1986: 424-433

High Performance Prolog, The Multiplicative Effect of Several Levels of ImplementationAlvin M. Despain, Yale N. Patt, Tep P. Dobry, Jung-Herng Chang, Wayne Citrin. compcon 1986: 178-185

Delay reduction using simulated annealingJonathan D. Pincus, Alvin M. Despain. dac 1986: 690-695 [doi]

1985

AND-Parallelism of Logic Programs Based on a Static Data Dependency AnalysisJung-Herng Chang, Alvin M. Despain, Doug DeGroot. compcon 1985: 218-226

Semi-Intelligent Backtracking of Prolog Based on Static Data Dependency AnalysisJung-Herng Chang, Alvin M. Despain. SLP 1985: 10-21

Fast fourier transform processors using Gaussian residue arithmeticAlvin M. Despain, Allen M. Peterson, Oscar S. Rothaus, Erling Wold. jpdc, 2(3):219-237, 1985. [doi]

Aquarius - A High Performance Computing System for Symbolic/Numeric ApplicationsAlvin M. Despain, Yale N. Patt. compcon 1985: 376-382

Performance Studies of a Prolog Machine ArchitectureTep P. Dobry, Alvin M. Despain, Yale N. Patt. isca 1985: 180-190

Compiling Prolog into microcode: a case study using the NCR/32-000Barry S. Fagin, Yale N. Patt, Vason P. Srini, Alvin M. Despain. micro 1985: 79-88 [doi]

1984

The Aquarius ProjectAlvin M. Despain, Yale N. Patt. compcon 1984: 364-368

Design decisions influencing the microarchitecture for a Prolog machineTep P. Dobry, Yale N. Patt, Alvin M. Despain. micro 1984: 217-231 [doi]

Pipeline and Parallel-Pipeline FFT Processors for VLSI ImplementationsErling Wold, Alvin M. Despain. TC, 33(5):414-426, 1984.

1979

Very Fast Fourier Transform Algorithms Hardware for ImplementationAlvin M. Despain. TC, 28(5):333-341, 1979.

1978

X-Tree: A Tree Structured Multi-Processor Computer ArchitectureAlvin M. Despain, David A. Patterson. isca 1978: 144-151

Communication In X-TREE, A Modular Multiprocessor SystemCarlo H. Séquin, Alvin M. Despain, David A. Patterson. acm 1978: 194-203 [doi]

1974

Fourier Transform Computers Using CORDIC IterationsAlvin M. Despain. TC, 23(10):993-1001, 1974. [doi]

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