Abstract is missing.
- Mapping HLL constructs into microcode for improved execution speedVeljko Milutinovic, D. Roberts, Kai Hwang. 2-11 [doi]
- A microcoded multiprocessor crossbar network communications controllerClifford L. Hall. 12-20 [doi]
- MASCO: An academic exercise in computer design using microprogrammingJack N. Fenner, Jeffery A. Schmidt, Houssam A. Halabi, Dharma P. Agrawal. 21-30 [doi]
- Architecture of a VLSI multiple ISA emulatorJ. L. Wilkes. 31-36 [doi]
- Applications of pipelining to firmwareDavid M. Proulx. 37-46 [doi]
- A chip set microarchitecture for a high-performance VAX implementationJohn F. Brown III, Richard L. Sites. 48-54 [doi]
- Software tools used in the development of a VLSI VAX MicrocomputerRobert Gries, James A. Woodward. 55-58 [doi]
- Design verification of a VLSI VAX microcomputerSridhar Samudrala, Charles Lo, John F. Brown III, Richard E. Calcagni. 59-63 [doi]
- A prototype engineering tester for microcode and hardware debuggingWill Sherwood. 64-69 [doi]
- Patchable control store for reduced microcode risk in a VLSI VAX microcomputerRichard E. Calcagni, Will Sherwood. 70-76 [doi]
- An improvement of trace scheduling for global microcode compactionBogong Su, Shiyuan Ding, Lan Jin. 78-85 [doi]
- Microassembly and area reduction techniques for PLA microcodeChristos A. Papachriston, James M. Reuter. 86-94 [doi]
- Compaction of two-level microprograms for a multiprocessor computerTakanobu Baba, Mitsuru Ikeda, Katsuhiro Yamazaki, Kenzo Okuda. 95-104 [doi]
- Improved instruction formation in the exhaustive local microcode compaction algorithmRichard P. Atkins. 105-111 [doi]
- The generation of simulator-based systems for microcode developmentColin C. Charlton, D. Jackson, Paul H. Leng. 114-121 [doi]
- TDL: A hardware/microcode test language interpreterGary Staas. 122-128 [doi]
- A "metasimulator" for microcoded processorsJ. Eldridge. 129-137 [doi]
- An algorithm for selection of migration candidatesBernhard Holtkamp, P. Wagner. 140-146 [doi]
- Migration implementation by integrating microprogramming and HLL programmingJuha-Matti Heimonen, Juha Heinänen. 147-154 [doi]
- An automatic migration scheme based on modular microcode and structured firmware sequencingChristos A. Papachristou, Venkata R. Immaneni, D. B. Sarma. 155-164 [doi]
- Transparent microprogramming in support of abstract type oriented dynamic vertical migrationEdward M. Carter, Robert I. Winner. 165-178 [doi]
- The implementation of the attributed recursive descent architecture in VAX-11/780 microcodeC. D. Ardoin, J. L. Linn, B. W. Reynolds. 179-189 [doi]
- Alternative proposals for implementing Prolog concurrently and implications regarding their respective microarchitecturesCarl Ponder, Yale N. Patt. 192-203 [doi]
- Sequential Prolog machine: Image and host architecturesEvan Tick. 204-216 [doi]
- Design decisions influencing the microarchitecture for a Prolog machineTep P. Dobry, Yale N. Patt, Alvin M. Despain. 217-231 [doi]
- Microcode verification using SDVS-the method and a case studyBeth Levy. 234-245 [doi]
- SDVS: A system for verifying microcode correctnessLeo Marcus, Stephen D. Crocker, Jaisook Landauer. 246-255 [doi]
- A new universal microprogram converterKazutoshi Takahashi, Etsuo Takahashi, Tatsushige Bitoh, Takao Sugimoto. 264-266 [doi]
- A retargetable compiler for a high-level microprogramming languagePeter Marwedel. 267-274 [doi]
- Global methods in the flow graph approach to retargetable microcode generationRobert A. Mueller, Joseph Varghese, Vicki H. Allan. 275-284 [doi]
- A survey of resource allocation methods in optimizing microcode compilersRobert A. Mueller, Michael R. Duda, Stephen M. O'Haire. 285-295 [doi]
- A model of clocked micro-architectures for firmware engineering and design automation applicationsSubrata Dasgupta. 298-308 [doi]
- Logic programming applied to hardware design specification and verificationDeepinder P. Sidhu. 309-313 [doi]
- An axiomatization of low-level parallelism in microarchitecturesWerner Damm. 314-323 [doi]