Abstract is missing.
- Weak Ordering - A New DefinitionSarita V. Adve, Mark D. Hill. 2-14
- Memory Consistency and Event Ordering in Scalable Shared-Memory MultiprocessorsKourosh Gharachorloo, Daniel Lenoski, James Laudon, Phillip B. Gibbons, Anoop Gupta, John L. Hennessy. 15-26
- Synchronization with Multiprocessor CachesJoonwon Lee, Umakishore Ramachandran. 27-37
- Dynamic Processor Allocation in Hypercube ComputersPo-Jen Chuang, Nian-Feng Tzeng. 40-49
- A New Approach to Fast Control of r2 x r2 3-Stage Benes Networks of r x r Crossbar SwitchesAbdou Youssef, Bruce W. Arden. 50-59
- Virtual-Channel Flow ControlWilliam J. Dally. 60-68
- Supporting Systolic and Memory Communciation in iWarpShekhar Borkar, Robert Cohn, George W. Cox, Thomas R. Gross, H. T. Kung, Monica S. Lam, Margie Levine, Brian Moore, Wire Moore, Craig Peterson, Jim Susman, Jim Sutton, John Urbanski, Jon A. Webb. 70-81
- Monsoon: An Explicit Token-Store ArchitectureGregory M. Papadopoulos, David E. Culler. 82-91
- The K2 Parallel Processor: Architecture and Hardware ImplementationMarco Annaratone, Marco Fillo, Kiyoshi Nakabayashi, Marc A. Viredaz. 92-101
- APRIL: A Processor Architecture for MultiprocessingAnant Agarwal, Beng-Hong Lim, David A. Kranz, John Kubiatowicz. 104-114
- PLUS: A Distributed Shared-Memory SystemRoberto Bisiani, Mosur Ravishankar. 115-124
- Adaptive Software Cache Management for Distributed Shared Memory ArchitecturesJohn K. Bennett, John B. Carter, Willy Zwaenepoel. 125-134
- An Empirical Evaluation of Two Memory-Efficient Directory MethodsBrian W. O Krafka, A. Richard Newton. 138-147
- The Directory-Based Cache Coherence Protocol for the DASH MultiprocessorDaniel Lenoski, James Laudon, Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy. 148-159
- The Performance Impact of Block Sizes and Fetch StrategiesSteven A. Przybylski. 160-169
- Reducing the Cost of Branches by Using RegistersJack W. Davidson, David B. Whalley. 182-191
- An Investigation of Static Versus Dynamic SchedulingCarl E. Love, Harry F. Jordan. 192-201
- VAX Vector ArchitectureDileep Bhandarkar, Richard Brunner. 204-215
- Multiple Instruction Issue in the NonStop Cyclone ProcessorRobert W. Horst, Richard L. Harris, Robert L. Jardine. 216-226
- Performance of an OLTP Application on Symmetry Multiprocessor SystemShreekant S. Thakkar, Mark Sweiger. 228-238
- The Impact of Synchronization and Granularity on Parallel SystemsDing-Kai Chen, Hong-Men Su, Pen-Chung Yew. 239-248
- Trace-Driven Simulations for a Two-Level Cache Design in Open Bus SystemsHakon O. Bugge, Ernst H. Kristiansen, Bjorn O. Bakka. 250-259
- Performance Measurement and Trace Driven Simulation of Parallel CAD and Numeric Applications on a Hypercube MulticomputerJiun-Ming Hsu, Prithviraj Banerjee. 260-269
- Generation and Analysis of Very Long Address TracesAnita Borg, Richard E. Kessler, David W. Wall. 270-279
- Fast Prolog with an Extended General Purpose ArchitectureBruce K. Holmer, Barton Sano, Michael J. Carlton, Peter Van Roy, Ralph Clarke Haygood, William R. Bush, Alvin M. Despain, Joan M. Pendleton, Tep P. Dobry. 282-291
- Balance in Architectural DesignSamuel Ho, Lawrence Snyder. 302-310
- A Study of I/O Behavior of Perfect Benchmarks on a MultiprocessorA. L. Narasimha Reddy, Prithviraj Banerjee. 312-321
- Maximizing Performance in a Striped Disk ArrayPeter M. Chen, David A. Patterson. 322-331
- A Distributed I/O Architecture for HARTSKang G. Shin, Greg Dykema. 332-342
- Boosting Beyond Static Scheduling in a Superscalar ProcessorMichael D. Smith, Monica S. Lam, Mark Horowitz. 344-354
- Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch BuffersNorman P. Jouppi. 364-373