Abstract is missing.
- A Model and an Architecture for a Relational Knowledge BaseHaruo Yokota, Hidenori Itoh. 2-9
- Implementation and Evaluation of a List-Processing-Oriented Data Flow MachineMakoto Amamiya, Masaru Takesue, Ryuzo Hasegawa, Hirohide Mikami. 10-19
- A New String Search Hardware Architecture for VLSIK. Takahashi, H. Yamada, H. Nagai, K. Matsumi. 20-27
- Parallel Algorithms and Architectures for Rule-Based SystemsAnoop Gupta, Charles Forgy, Allen Newell, Robert G. Wedig. 28-37
- Concert: Design of a Multiprocessor Development SystemRobert H. Halstead Jr., Thomas L. Anderson, Randy B. Osborne, Thomas L. Sterling. 40-48
- Memory Requirements for Balanced Computer ArchitecturesH. T. Kung. 49-54
- Graph Allocation in Static Dataflow SystemsYang-Chang Hong, Thomas H. Payne, Le Baron O. Ferguson. 55-64
- Software Implementation of a Recursive Fault Tolerance Algorithm on a Network of ComputersPrathima Agrawal, Rakesh Agrawal. 65-72
- Fast Object-Oriented Procedure Calls: Lessons from the Intel 432Edward F. Gehringer, Robert P. Colwell. 92-101
- On Coupling Many Small Systems for Transaction ProcessingDaniel M. Dias, Balakrishna R. Iyer, Philip S. Yu. 104-110
- Performance Measurement of Paging Behavior in Multiprogramming SystemsMohammad Malkawi, Janak H. Patel. 111-118
- ATUM: A New Technique for Capturing Address Traces Using MicrocodeAnant Agarwal, Richard L. Sites, Mark Horowitz. 119-127
- Experimenting With EPILOG: Some Results and Preliminary ConclusionsMichael J. Wise. 130-139
- A Unification Processor Based on a Uniformly Structured Cellular HardwareYasuro Shobatake, Hideo Aiso. 140-148
- The Architecture and Preliminary Evaluation Results of the Experimental Parallel Inference Machine PIM-DNoriyoshi Ito, Masatoshi Sato, Eiji Kuno, Kazuaki Rokusawa. 149-156
- An Efficient Routing Control Unit for the SIGMA Network E(4)André Seznec. 158-168
- REYSM, A High Performance, Low Power Multi-Microprocessor BusJean-Daniel Nicoud, K. Skala. 169-174
- The Extra Stage Gamma NetworkKyungsook Y. Lee, Wael Hegazy. 175-182
- Evaluation of the FACOM ALPHA Lisp MachineMasanobu Yuhara, Akira Hattori, Masashi Niwa, Mitsuhiro Kishimoto, Hiromu Hayashi. 184-190
- An Architecture for Efficient Lisp List AccessAndrew R. Pleszkun, Matthew Thazhuthaveetil. 191-198
- A Functional Level Simulation Engine of MAN-YO: A Special Purpose Parallel Machine for Logic Design AutomationToshiyuki Nakata, Nobuhiko Koike. 202-208
- Exploiting Parallelism in a Switch-Level Simulation MachineEdward H. Frank. 209-215
- A Hardware Accelerator for Speech Recognition AlgorithmsThomas S. Anantharaman, Roberto Bisiani. 216-223
- Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific ComputationsToshio Shimada, Kei Hiraki, Kenji Nishida, Satoshi Sekiguchi. 226-234
- Stored Data Structures on the Manchester Dataflow MachineJohn Sargeant, Chris C. Kirkham. 235-242
- A Salable Dataflow Structure StoreK. Kawakami, John R. Gurd. 243-250
- AT2=O(N log4 N), T=O(log N) Fast Fourier Transform in a Light Connected 3-Dimensional VLSIMakoto Hasegawa, Yoshiharu Shigei. 252-260
- Modular Architecture for High Performance Implementation of FFT AlgorithmKrzysztof Sapiecha, R. Jarocki. 261-270
- Computing Size-Independent Matrix Problems on Systolic Array ProcessorsJuan J. Navarro, José M. Llabería, Mateo Valero. 271-278
- A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp MachinesShinji Tomita, Kiyoshi Shibayama, Toshiyuki Nakata, Shinji Yuasa, Hiroshi Hagiwara. 280-289
- VLSI Oriented Asynchronous ArchitectureMasaharu Hirayama. 290-296
- HPSm, a High Performance Restricted Data Flow Architecture Having Minimal FunctionalityWen-mei W. Hwu, Yale N. Patt. 297-306
- Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage SchemeDavid T. Harper III, J. Robert Jump. 324-328
- Pseudo MIMD Array Processor - AAP2Toshio Kondo, Toshio Tsuchiya, Yoshihiro Kitamura, Yoshi Sugiyama, Takashi Kimura, Takayoshi Nakashima. 330-337
- Scan Line Array Processors for Image ComputationAllan L. Fisher. 338-345
- Warp Architecture and ImplementationMarco Annaratone, Emmanuel A. Arnould, Thomas R. Gross, H. T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, Jon A. Webb. 346-356
- Software-Controlled Caches in the VMP MultiprocessorDavid R. Cheriton, Gert Slavenburg, Patrick D. Boyle. 366-374
- Highly Concurrent Scalar ProcessingPeter Y.-T. Hsu, Edward S. Davidson. 386-395
- Reducing the Cost of BranchesScott McFarling, John L. Hennessy. 396-403
- Optimal Pipelining in SupercomputersSteven R. Kunkel, James E. Smith. 404-411
- A Class of Compatible Cache Consistency Protocols and their Support by the IEEE FuturebusPaul Sweazey, Alan Jay Smith. 414-423
- Multiprocessor Cache Synchronization: Issues, Innovations, EvolutionPhilip Bitar, Alvin M. Despain. 424-433
- Memory Access Buffering in MultiprocessorsMichel Dubois, Christoph Scheurich, Faye A. Briggs. 434-442
- Evaluation of the SPUR Lisp ArchitectureGeorge S. Taylor, Paul N. Hilfinger, James R. Larus, David A. Patterson, Benjamin G. Zorn. 444-452