George S. Taylor - researchr alias

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Viewing Publication 1 - 18 from 18

2003

Security Evaluation of Asynchronous CircuitsJacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor. ches 2003: 137-151 [doi]

Balanced self-checking asynchronous logic for smart card applicationsSimon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier. mam, 27(9):421-430, 2003. [doi]

2002

Improving Smart Card Security Using Self-Timed CircuitsSimon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor. async 2002: 211 [doi]

Point to Point GALS InterconnectGeorge S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson. async 2002: 69-75 [doi]

2000

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous SystemsSimon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson. iccd 2000: 73 [doi]

An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed SystemsGeorge S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson. async 2000: 45-51 [doi]

1998

Reduced complexity two-phase micropipeline latch controllerGeorge S. Taylor, Gerard M. Blair. jssc, 33(10):1590-1593, 1998. [doi]

1989

A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processingDavid D. Lee, Shing I. Kong, Mark D. Hill, George S. Taylor, David A. Hodges, Randy H. Katz, David A. Patterson 0001. jssc, 24(6):1688-1698, December 1989. [doi]

1987

Fast multiply and divide for a VLSI floating-point unitBidyut Kumar Bose, Li-fan Pei, George S. Taylor, David A. Patterson. arith 1987: 87-94 [doi]

1986

Evaluation of the SPUR Lisp ArchitectureGeorge S. Taylor, Paul N. Hilfinger, James R. Larus, David A. Patterson, Benjamin G. Zorn. isca 1986: 444-452

An In-Cache Address Translation MechanismDavid A. Wood, Susan J. Eggers, Garth A. Gibson, Mark D. Hill, Joan M. Pendleton, Scott A. Ritchie, George S. Taylor, Randy H. Katz, David A. Patterson. isca 1986: 358-365

1985

The Magic VLSI Layout SystemJohn K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor. dt, 2(1):19-30, 1985. [doi]

Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIBGeorge S. Taylor. arith 1985: 64-71 [doi]

1984

Magic: A VLSI layout systemJohn K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor. dac 1984: 152-159 [doi]

Magic's incremental design-rule checkerGeorge S. Taylor, John K. Ousterhout. dac 1984: 160-165 [doi]

1983

Arithmetic on the ELXSI System 6400George S. Taylor. arith 1983: 110-115 [doi]

1981

Compatible hardware for division and square rootGeorge S. Taylor. arith 1981: 127-134 [doi]

VAX hardware for the proposed IEEE floating-point standardGeorge S. Taylor, David A. Patterson. arith 1981: 190-196 [doi]

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