Abstract is missing.
- Some optimal schemes for ALU implementation in VLSI technologyVojin G. Oklobdzija, Earl R. Barnes. 2-8 [doi]
- Regular, area-time efficient carry-lookahead addersTin-Fook Ngai, Mary Jane Irwin. 9-15 [doi]
- A multioperand two's complement addition algorithmHideaki Kobayashi. 16-19 [doi]
- Improved normalization results for digit on-line arithmeticRichard J. Zaccone, Jesse L. Barlow. 20-27 [doi]
- Efficient serial-parallel arrays for multiplication and additionLuigi Ciminiera, Angelo Serra. 28-35 [doi]
- Design of a fast inner product processorScobie Philip Smith, Hwa C. Torng. 38-43 [doi]
- Design for a recursive parallel multiplierRenato de Mori, Régis Cardin. 44-50 [doi]
- A division algorithm with prediction of quotient digitsMilos D. Ercegovac, Tomás Lang. 51-56 [doi]
- Fast multipliers for two's-complement numbers in serial formLuigi Dadda. 57-63 [doi]
- Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIBGeorge S. Taylor. 64-71 [doi]
- Axiomatizations of floating point arithmeticsWlodzimierz Zadrozny. 74-81 [doi]
- High-speed computation of unary functionsM. Ohhashi, R. K. Schneider. 82-85 [doi]
- Floating-point arithmetic on a reduced-instruction-set processorThomas Gross. 86-92 [doi]
- VLSI floating-point processorsJan Fandrianto, B. Y. Woo. 93-100 [doi]
- A family of CMOS floating point arithmetic chipsJohn A. Eldon. 101-107 [doi]
- Systolic polynomial evaluation and matrix multiplication with multiple precisionJonathan Schaeffer, Darrell Makarenko. 110-117 [doi]
- A systolic algorithm for integer GCD computationR. P. Brent, H. T. Rung. 118-125 [doi]
- Algorithm partition for a fixed-size VLSI architecture using space-time domain expansionHeng-Da Cheng, King-sun Fu. 126-132 [doi]
- Prime Factor DFT parallel processor using wafer scale integrationEdward T. Chow, Dan I. Moldovan. 133-140 [doi]
- The modified CORDIC algorithmAsif Naseem, P. David Fisher. 144-152 [doi]
- Polynomial TransformerTakakazu Kurokawa, Hideo Aiso. 153-158 [doi]
- The VLSI implementation of a square root algorithmJaisimha Bannur, A. Varma. 159-165 [doi]
- A pipeline architecture for computing cumulative hypergeometric distributionsXiaobo Li, Lionel M. Ni. 166-172 [doi]
- Squarers for binary numbers in serial formLuigi Dadda. 173-179 [doi]
- Multi - Input residue arithmetic utilizing read - Only associative memoryChristos A. Papachristou. 182-188 [doi]
- Binary paradigm and systolic array implementation for residue arithmeticDavid Y. Y. Yun, Chang N. Zhang. 189-193 [doi]
- Rationally biased arithmeticWarren E. Ferguson, David W. Matuja. 194-202 [doi]
- VLSI residue multiplier modulo a Fermat numberIrving S. Reed, Trieu-Kien Truong, J. J. Chang, Howard M. Shao, In-Shek Hsu. 203-206 [doi]
- Finite precision lexicographic continued fraction number systemsPeter Kornerup, David W. Matula. 207-213 [doi]
- Three dimensional IC's and an application to high speed image processorKenji Taniguchi 0001. 216-222 [doi]
- Arithmetic for high speed FFT implementationEarl E. Swartzlander Jr., John A. Eldon. 223-230 [doi]
- The design of a vector-radix 2DFFT chipWentai Liu, J. C. Duh, Daniel E. Atkins. 231-236 [doi]
- PAPIA: Pyramidal architecture for parallel image analysisVirginio Cantoni, Marco Ferretti, Stefano Levialdi, Renato Stefanelli. 237-242 [doi]
- A more efficient residue arithmetic implementation of the FFTFred J. Taylor. 243-249 [doi]
- On the structure of parallelism in a highly concurrent PDE solverDennis Gannon. 252-259 [doi]
- A parallel method for computing the generalized singular value decompositionFranklin T. Luk. 260-265 [doi]
- Multiprocessors for evaluating compound arithmetic functionsKai Hwang, Zhiwei Xu. 266-275 [doi]
- Multiple error correction and additive overflow detection with magnitude indices in residue codeSaroj Kaushik. 278-284 [doi]
- Arithmetic algorithms for operands encoded in two-dimensional low-cost arithmetic error codesAlgirdas Avizienis. 285-292 [doi]
- A class of A(N + C) codes and its propertiesT. R. N. Rao, Kasem Vathanvit. 293-294 [doi]
- Maximal redundancy signed-digit systemsTien Chi Chen. 296-299 [doi]
- Higher Order Computer ArithmeticSiegfried M. Rump. 302-308 [doi]
- DRAFT: A dynamically reconfigurable processor for integer arithmeticDonald M. Chiarulli, Walter G. Rudd, Duncan A. Buell. 309-317 [doi]
- ACRITH: High-Accuracy Arithmetic an advanced tool for numerical computationJ. Hartmut Bleher, A. E. Roeder, Siegfried M. Rump. 318-321 [doi]
- Anomalies in the IBM ACRITH packageWilliam Kahan, E. LeBlanc. 322-331 [doi]
- Complex interval division with maximum accuracyR. Lohner, Jürgen Wolff von Gudenberg. 332-336 [doi]
- A fast algorithm for the symmetric eigenvalue problemJack J. Dongarra, Danny C. Sorensen. 337-342 [doi]