Howard M. Shao - researchr alias

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Viewing Publication 1 - 10 from 10

1988

On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic ArraysHoward M. Shao, Irving S. Reed. TC, 37(10):1273-1280, 1988.

A Pipeline Design of a Fast Prime Factor DFT on a Finite FieldTrieu-Kien Truong, Irving S. Reed, In-Shek Hsu, Hsuen-Chyun Shyu, Howard M. Shao. TC, 37(3):266-273, 1988.

1986

A single chip VLSI Reed-Solomon decoderHoward M. Shao, Trieu-Kien Truong, In-Shek Hsu, Leslie J. Deutsch, Irving S. Reed. icassp 1986: 2151-2154 [doi]

1985

The VLSI design of a single chip for the multiplication of integers modulo a Fermat numberJaw John Chang, T. K. Truong, Howard M. Shao, Irving S. Reed, In-Shek Hsu. tsp, 33(6):1599-1602, 1985. [doi]

The VLSI design of a single chip for the multiplication of integers modulo a fermat numberJaw John Chang, Trieu-Kien Truong, Howard M. Shao, Irving S. Reed, In-Shek Hsu. icassp 1985: 1388-1391 [doi]

VLSI residue multiplier modulo a Fermat numberIrving S. Reed, Trieu-Kien Truong, J. J. Chang, Howard M. Shao, In-Shek Hsu. arith 1985: 203-206 [doi]

A VLSI Design of a Pipeline Reed-Solomon DecoderHoward M. Shao, Trieu-Kien Truong, Leslie J. Deutsch, Joseph H. Yuen, Irving S. Reed. TC, 34(5):393-403, 1985.

A VLSI design of a pipeline Reed-Solomon decoderHoward M. Shao, Trieu-Kien Truong, Leslie J. Deutsch, Joseph H. Yuen, Irving S. Reed. icassp 1985: 1404-1407 [doi]

VLSI Architectures for Computing Multiplications and Inverses in ::::GF::::(2:::::::m:::::::)Charles C. Wang, Trieu-Kien Truong, Howard M. Shao, Leslie J. Deutsch, Jim K. Omura, Irving S. Reed. TC, 34(8):709-717, 1985.

1983

A Parallel Architecture for Digital Filtering Using Fermat Number TransformsTrieu-Kien Truong, Irving S. Reed, C.-S. Yeh, Howard M. Shao. TC, 32(9):874-877, 1983.

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