Abstract is missing.
- Formal Verification of Safety Properties in Timed Circuits2-11 [doi]
- On Directed Transformations of Delay-Insensitive Specifications, Alternations and Dynamic NondeterminismWillem C. Mallon. 12-22 [doi]
- Composing SnippetsIgor Benko, Jo C. Ebergen. 23 [doi]
- Applying Asynchronous Circuits in Contactless Smart CardsJoep L. W. Kessels, Gerrit den Besten, Ad M. G. Peeters, Torsten Kramer, Volker Timm. 36-44 [doi]
- An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed SystemsGeorge S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson. 45-51 [doi]
- Practical Design of Globally-Asynchronous Locally-Synchronous SystemsJens Muttersbach, Thomas Villiger, Wolfgang Fichtner. 52 [doi]
- CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length DecoderMarly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri. 62-72 [doi]
- DUDES: A Fault Abstraction and Collapsing Framework for Asynchronous CircuitsPhilip P. Shirvani, Subhasish Mitra, Jo C. Ebergen, Marly Roncken. 73 [doi]
- Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDLIvan Blunno, Luciano Lavagno. 84-92 [doi]
- High-Level Asynchronous System Design Using the ACK FrameworkHans M. Jacobson, Erik Brunvand, Ganesh Gopalakrishnan, Prabhakar Kudva. 93-103 [doi]
- Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level SynthesisEuiseok Kim, Jeong-Gun Lee, Dong-Ik Lee. 104-113 [doi]
- Asynchronous Design Using Commercial HDL Synthesis ToolsMichiel M. Ligthart, Karl Fant, Ross Smith, Alexander Taubin, Alex Kondratyev. 114
- Priority ArbitersAlexandre V. Bystrov, D. J. Kinniment, Alexandre Yakovlev. 128-137 [doi]
- Simple Circuits that Work for Complicated ReasonsCharles E. Molnar, Ian W. Jones. 138-149 [doi]
- Asynchronous Communication Mechanisms Using Self-Timed CircuitsFei Xia, Alexandre Yakovlev, Delong Shang, Alexandre V. Bystrov, Albert Koelmans, D. J. Kinniment. 150 [doi]
- AMULET3i - An Asynchronous System-on-ChipJim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, J. V. Woods, Jianwei Liu, O. Petli. 162-175 [doi]
- An Instruction Buffer for a Low-Power DSPMike J. G. Lewis, L. E. M. Brackenbury. 176 [doi]
- VLSI System Design Using Asynchronous Wave Pipelines: A 0.35?m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem ChipO. Hauck, A. Katoch, Sorin A. Huss. 188 [doi]
- High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic DatapathsMontek Singh, Steven M. Nowick. 198 [doi]
- Low-Latency Asynchronous FIFO s Using Token RingsTiberiu Chelcea, Steven M. Nowick. 210 [doi]