Ivan Blunno, Luciano Lavagno. Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. In 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel. pages 84-92, IEEE Computer Society, 2000. [doi]
Abstract is missing.