Ken S. Stevens - researchr alias

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Viewing Publication 1 - 14 from 14

2011

Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and SystemsKen S. Stevens, Alexandre Yakovlev. iet-cdt, 5(4):316-317, 2011. [doi]

2009

Automatic synthesis of computation interference constraints for relative timing verificationYang Xu, Ken S. Stevens. iccd 2009: 16-22 [doi]

2007

Guest Editors Introduction: GALS Design and ValidationMichael Kishinevsky, Sandeep K. Shukla, Ken S. Stevens. dt, 24(5):414-416, 2007. [doi]

2006

PrefaceKen S. Stevens, Sandeep K. Shukla, Montek Singh, Jean-Pierre Talpin. ENTCS, 146(2):1-3, 2006. [doi]

2003

Relative timing [asynchronous design]Ken S. Stevens, Ran Ginosar, Shai Rotem. tvlsi, 11(1):129-140, 2003. [doi]

2002

Relative Timing Based Verification of Timed Circuits and SystemsPeter A. Beerel, Ken S. Stevens, Hoshik Kim. async 2002: 115 [doi]

Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptionsJordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev. tcad, 21(2):109-130, 2002. [doi]

2000

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length DecoderMarly Roncken, Ken S. Stevens, Rajesh Pendurkar, Shai Rotem, Parimal Pal Chaudhuri. async 2000: 62-72 [doi]

Fsimac: a fault simulator for asynchronous sequential circuitsSusmita Sur-Kolay, Marly Roncken, Ken S. Stevens, Parimal Pal Chaudhuri, Rob Roy. ats 2000: 114-119 [doi]

1999

1998

Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode CircuitsWei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun. async 1998: 80 [doi]

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