Abstract is missing.
- A FIFO Data Switch Design ExperimentWilliam S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland. 4 [doi]
- ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous MicroprocessorMarc Renaudin, Pascal Vivet, Frédéric Robin. 22-31 [doi]
- A Low-Power, Low-Noise, Configurable Self-Timed DSPN. C. Paver, P. Day, C. Farnsworth, D. L. Jackson, W. A. Lien, Jianwei Liu. 32-42 [doi]
- A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded ProcessorsMartin Benes, Steven M. Nowick, Andrew Wolfe. 43 [doi]
- An Implicit Method for Hazard-Free Two-Level Logic MinimizationMichael Theobald, Steven M. Nowick. 58-69 [doi]
- Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode CircuitsKevin W. James, Kenneth Y. Yun. 70-79 [doi]
- Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode CircuitsWei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun. 80 [doi]
- An Asynchronous Low-Power 80C51 MicrocontrollerHans van Gageldonk, Kees van Berkel, Ad M. G. Peeters, Daniel Baumann, Daniel Gloor, Gerhard Stegmann. 96-107 [doi]
- The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor CoreKåre T. Christensen, Peter Jensen, Peter Korger, Jens Sparsø. 108 [doi]
- Asynchronous Macrocell Interconnect using MARBLEW. J. Bainbridge, Stephen B. Furber. 122-132 [doi]
- An Asynchronous PRBS Error Checker for Testing High-Speed Self-Clocked Serial LinksP. T. Røine. 133 [doi]
- Verifying a Self-Timed DividerTarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet. 146-158 [doi]
- Verification of Speed-Dependences in Single-Rail Handshake CircuitsRadu Negulescu, Ad M. G. Peeters. 159 [doi]
- Analyzing Specifications for Delay-Insensitive CircuitsTom Verhoeff. 172-183 [doi]
- Building Finite Automata from DI SpecificationsWillem C. Mallon, Jan Tijmen Udding. 184-193 [doi]
- Membership Test Logic for Delay-Insensitive CodesStanislaw J. Piestrak. 194 [doi]
- Towards Asynchronous A-D ConversionD. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao. 206-215 [doi]
- A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space ApplicationsBruce W. Hunt, Kenneth S. Stevens, Bruce W. Suter, Donald S. Gelosh. 216-223 [doi]
- An Asynchronous 2-D Discrete Cosine Transform ChipRoss Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang. 224 [doi]
- Predicting Performance of Micropipelines Using Charlie DiagramsJo C. Ebergen, Scott Fairbanks, Ivan E. Sutherland. 238-246 [doi]
- Accelerating Markovian Analysis of Asynchronous Systems using String- based State CompressionAiguo Xie, Peter A. Beerel. 247 [doi]
- Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven LogicYoshio Kameda, Stanislav Polonsky, Masaaki Maezawa, Takashi Nanya. 262-273 [doi]
- Asynchronous Circuits and Systems in Superconducting RSFQ Digital TechnologyZ. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno. 274 [doi]