Abstract is missing.
- The design of two easily-testable VLSI array multipliersF. Joel Ferguson, John Paul Shen. 2-9 [doi]
- A comparison of ALU structures for VLSI technologyShauchi Ong, Daniel E. Atkins. 10-16 [doi]
- On design and performance of VLSI based parallel multiplierDharma P. Agrawal, Girish C. Pathak, Nikunja K. Swain, Bhuwan K. Agrawal. 17-21 [doi]
- On fast binary addition in MDS TechnologiesLeonidas J. Guibas, Jean Vuillemin. 22 [doi]
- Sign detection in Non-Redundant Residue Number System with reduced informationSaroj Kaushik. 24-28 [doi]
- Representation and processing of fractions in a residue systemDilip K. Banerji, Saroj Kaushik. 29-36 [doi]
- Systems of numerationAviezri S. Fraenkel. 37-42 [doi]
- A multiplier with multiple error correction capabilityMarco Annaratone, Renato Stefanelli. 44-51 [doi]
- Some schemes for fast serial input multipliersLuigi Dadda. 52-59 [doi]
- Fast iterative multiplying arrayLuigi Ciminiera, Angelo Serra. 60-66 [doi]
- Conditions for the distributivity of multiplication with respect to set addition and their effect on the design of array multipliersJames E. Robertson. 67-71 [doi]
- Experience with a high level language that supports interval arithmeticRonald Morrison, A. J. Cole, Peter J. Bailey, M. A. Wolfe, J. M. Shearer. 74-78 [doi]
- ADA floating-point arithmetic as a basis for portable numerical softwarePeter J. L. Wallis. 79-81 [doi]
- On the numerical algorithms formulated in computer arithmeticSvetoslav Markov. 82-85 [doi]
- A numeric error algebraW. S. Brown, C. S. Wetherell. 86-91 [doi]
- A higher-radix division with simple selection of quotient digitsMilos D. Ercegovac. 94-98 [doi]
- Square-root algorithms for high-speed digital circuitsStanislaw Majerski. 99-102 [doi]
- Some tricks of the (floating point) tradeJ. B. Gosling. 103 [doi]
- On bit sequential multipliersRavindra V. Donthi, Mohammed Saleem, Harpreet Singh. 104-108 [doi]
- Arithmetic on the ELXSI System 6400George S. Taylor. 110-115 [doi]
- Matrix multiplication on LUCASLennart Ohlsson, Bertil Svensson. 116-122 [doi]
- Multi-operand associative arithmeticIsaac D. Scherson, Smil Ruhman. 123-129 [doi]
- An IEEE floating point arithmetic implementationKari Johnsen. 130-135 [doi]
- Fast matrix solver in GF(2)Yoshiyasu Takefuji, Takakazu Kurokawa, Hideo Aiso. 138-143 [doi]
- Vector reduction methods for arithmetic pipelinesLionel M. Ni, Kai Hwang. 144-150 [doi]
- On-line multiplicative normalizationAksenti L. Grnarov, Milos D. Ercegovac. 151-155 [doi]
- Numerical limitations on the design of digit online networksRobert Michael Owens, Mary Jane Irwin. 156-161 [doi]
- Arithmetic for a high-speed adaptive learning network elementHideaki Kobayashi, Ronald D. Bonnell. 164-168 [doi]
- Applications for arithmetic error codes in large, high-performance computersAlgirdas Avizienis, C. S. Raghavendra. 169-173 [doi]
- Models for VLSI implementation of residue number system arithmetic modulesMagdy A. Bayoumi, Graham A. Jullien, William C. Miller. 174-182 [doi]
- Continued fractions for high-speed and high-accuracy computer arithmeticRobert B. Seidensticker. 184-193 [doi]
- Floating-point recurring rational arithmetic systemKaoru Yoshida. 194-200 [doi]
- An order preserving finite binary encoding of the rationalsDavid W. Matula, Peter Kornerup. 201-209 [doi]
- A unified view of approximate rational arithmetic and rational interpolationAlfonso Miola. 210-220 [doi]